Semiconductor memory device having memory cell block...

Details Semiconductor memory device having memory cell block... Semiconductor memory device having memory cell block...

2001-12-28

2003-06-17

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S203000, C365S189070, C365S233100, C365S194000

Reexamination Certificate

active

06580656

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device having a plurality of memory cell blocks controlled by a memory cell block activation control circuit, and a method for controlling activation of memory cell blocks which can improve operation speed, by controlling activation timing of the plurality of memory cell blocks and reducing unnecessary delay time in the memory block activation.
2. Description of the Background Art
A data read/write operation of a general semiconductor memory device having a plurality of memory cell blocks will be explained.
In the read operation, one memory cell block is selected from the plurality of memory cell blocks according to a block select address. The selected memory cell block is activated.
In the activated memory cell block, when a row address strobe signal /RAS is activated in a low level and a row address is transmitted at the same time, one word line corresponding to the row address is activated, and thus data stored in a plurality of cells connected to the activated word line are transmitted to bit lines. A minute electrical signal of each bit line is sensed and amplified by a sense amp.
The data amplified by the sense amp on the bit line corresponding to a column address is externally outputted in response to activation of a column address strobe signal /CAS. Here, the block select address is generated, by using the most significant address among the row addresses.
After the data stored in the selected cell is outputted, in accordance with the row address and the column address, the enabled word line is precharged, and returns to an inactivation state. A predetermined time tRP may be set up in design between the start of a precharge state and the end of the precharge state.
For example, when the memory cell block indicated by the block select address is activated, and the word line corresponding to the row address is activated, no operation can be performed for the time tRP necessary for precharging the activated word line, which results in time consumption. That is, although one word line is activated and the read or write operation is performed and ended, another word line is not activated during tRP necessary to precharge the activated word line. During the unnecessarily repeated precharge operation, the DRAM maintains a stand-by mode. Accordingly, it is impossible to achieve high-speed operation.
The precharge time tRP is determined by specification in designing the semiconductor memory device. Although the memory cell block does not need to be precharged, the memory cell block is activated after the standby time for as long as the precharge time tRP, thereby unnecessarily increasing the operation delay time.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to achieve a high-speed operation by reducing a delay time in activation of a memory cell block.
In order to achieve the above-described object of the invention, there is provided a semiconductor memory device having a memory cell block activation control circuit, including: a block activation signal generating means for generating a block activation signal which activates a plurality of memory cell blocks by using a row active signal and a row address; and a block activation control means for outputting a block activation control signal which controls activation timing of the plurality of memory cell blocks by using the block activation signal and the row active signal.
There is also provided a method for controlling activation of memory cell blocks of a semiconductor memory device, including the steps of: checking whether a currently activated memory cell block is identical to a previously activated memory cell block; activating the current memory cell block after a predetermined delay time, when the currently activated memory cell block is identical to the previously activated memory cell block; and activating the current memory cell block without delay, when the currently activated memory cell block is different from the previously activated memory cell block.


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patent: 6094398 (2000-07-01), Rieger
patent: 6154414 (2000-11-01), Lee
patent: 6344990 (2002-02-01), Matsumiya et al.
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patent: 6377506 (2002-04-01), Kitazawa
patent: 6381191 (2002-04-01), Ooishi

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