Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2001-01-03
2003-11-11
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S675000, C257S712000, C257S777000
Reexamination Certificate
active
06646334
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package, and more particularly, to a stacked chip-size semiconductor package which is capable of performing a molding process and a stacking process by a strip unit enhancing productivity, and capable of attaching a heat sink in a strip form enhancing heat releasing capacity.
2. Description of the Background Art
As electronic equipment such as laptop computers or mobile phones are in the tendency of becoming smaller and lighter on a gradual basis, a necessity for reducing the area occupied by a semiconductor package has been gradually increased.
In order to meet the requirement, a method for reducing the area of the package and a method for stacking several semiconductor chips on a single semiconductor package are used.
FIG. 1
illustrates a structure of a stacked BLP (bottom leaded package) in accordance with a conventional art.
As shown in the drawing, the first chip
1
and the second chip
2
respectively are stacked to face a chip pad (not shown) formed on respective upper surface thereof
A first package
10
a
of the conventional stacked BLP is constructed as follows:
The plurality of first leads
3
attached on the upper surface of the first chip i by means of the insulating tape
7
are respectively connected to the chip pad (not shown) of the upper surface of the first chip through the wire
8
.
Each of the first leads includes an inner lead formed by a first portion
3
a
attached on the first chip, a second portion
3
b
upwardly bent from the first portion
3
a
, and a third portion
3
c
extended from one end of the second portion
3
b
and parallel to the first portion
3
a
, and an ‘L’-shaped outer lead formed by the fourth portion
3
d
downwardly bent from the third portion
3
c
and a fifth portion
3
e
extended from one end of the fourth portion
3
d
and parallel to the first portion
3
a
and the third portion
3
c.
The first chip
1
and the inner lead portion of the first lead are sealed by a first molding compound
6
a
, while the opposite side surface to the first chip
1
of the third portion
3
c
of the first lead is not sealed by the first molding compound
6
a
. The outer lead portion of the first lead
3
is outwardly protruding from the first molding compound
6
a.
A second package
10
b
of the conventional stacked BLP is constructed as follows:
A plurality of second leads
4
are attached on the upper surface of the second chip
2
, facing the first chip
1
, by the insulating tape. The respective second leads
4
are electrically connected to the chip pad (not shown) on the upper surface of the second chip through the wire
8
.
The second lead
4
includes a first portion
4
a
attached on the second chip
2
, a second portion
4
b
downwardly bent from the first portion
4
a
and a third portion extended from one end of the second portion
4
b
and parallel to the first portion
4
a.
The second chip
2
and the second lead
4
are sealed by the second molding compound
6
b
, while the opposite side surface to the second chip
2
of the third portion
4
C of the second lead is not sealed by the second molding compound
6
b.
In the first package
10
a
and the second package
10
b
of the stacked BLP of the conventional art, the non-sealed portion of the third portion
3
c
of the first lead and the non-sealed portion of the third portion
4
c
of the second lead are respectively attached, electrically connected and stacked by the solder
5
.
However, regarding the stacked package of the conventional art described as above, since the first package
10
a
and the second package
10
b
are separately fabricated and stacked by using a stack jig by individual unit, productivity is degraded.
In addition, since the area for releasing the heat generated when the chip is operated is limited, an additional heat sink needs to be attached outside the stacked package so as to improve an efficiency of heat release.
Also, since the package includes the outer leads, it is impossible to reduce the area of the package to as small as the chip size.
Moreover, in case that a package is desired to be additionally stacked on the upper surface of the second package
10
b
of the stacked package, since the electrical connection between the package is difficult, it is difficult to stack more than two chips.
SUMMARY OF THE INVENTION
Therefore, one aspect of the invention is to provide a stacked semiconductor package for which a molding process and a stacking process are performed by using a strip unit, thereby reducing the defects caused in stacking and improving productivity.
Another aspect of the invention is to provide a stacked semiconductor package in which a heat sink is included in a stacked package, thereby improving the heat releasing capacity of the stacked package.
Another aspect of the invention is to provide a stacked semiconductor package which avoids use of external leads as an external terminal thereby reducing the package size to be as small as the chip size.
The present invention also provides a stacked semiconductor package that is capable of stacking more than three chips.
To achieve these and other advantages and in accordance with the one of the purposes of the invention, as embodied and broadly described herein, there is provided a stacked semiconductor package including: a first chip; a plurality of first leads of which one side of the first leads is attached to the first chip by an insulating adhesive member and electrically connected to the first chip; a first molding compound for sealing the first chip and the first leads, including a hole for exposing a predetermined portion of each of the first leads, and exposing a predetermined portion of the side opposite to the hole of the each of the first leads; a first conductive portion formed within the hole included in the first molding compound; an external terminal electrically connected to the first conductive portion; a second chip; a plurality of second leads attached on the second chip by the insulating adhesive member, and being electrically connected to the second chip; a second molding compound for sealing the second chip and the second leads, and exposing a predetermined portion of the second leads; a plurality of conductive connection units for electrically connecting the exposed side of the predetermined portion of the second leads and the exposed side of the predetermined portion of the first leads; and a heat sink being attached between the first molding compound and the second molding compound, connected to the plurality of conductive connection units, and having a side exposed outwardly.
In order to attain the above results, there is also provided a method for fabricating a semiconductor package including the steps of: preparing a first strip including a plurality of first leads; attaching a first chip onto the first leads by using an insulating adhesive member; electrically connecting the first chip and the first leads; molding the first chip and the first strip by using a first mold and a second mold having a plurality of protrusions, and sealing the first leads except for a predetermined region thereof; forming a first conductive portion in a hole formed by the protrusion of the second mold; preparing a second strip including a plurality of second leads; attaching a second chip to the second leads by using the insulating adhesive member; electrically connecting the second chip and the second lead; molding the second chip and the second strip by using the first mold and the second mold having the plurality of protrusions, and sealing the second lead except for the predetermined region thereof; forming a second conductive portion in the hole formed by the protrusion of the second mold; facing the first lead and the predetermined region of the second lead; positioning a heat sink strip including solder balls formed spaced apart at predetermined intervals between the first leads and the second leads; arranging the first leads, the second leads and the solder balls in a row in
Brophy Jamie L.
Hyundai Electronics Industries Co,. Ltd.
Morgan & Lewis & Bockius, LLP
Zarabian Amir
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