Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2002-03-19
2003-11-11
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230030, C365S063000
Reexamination Certificate
active
06646954
ABSTRACT:
FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
[Not Applicable]
SEQUENCE LISTING [Not Applicable]
BACKGROUND OF THE INVENTION
One embodiment of the present invention relates to memory devices. In particular, one embodiment of the present invention relates to self-timed blocks in synchronously controlled semiconductor memory devices.
Memory structures have become integral parts of modern VLSI systems, including digital line processing systems. Although typically it is desirable to incorporate as many memory cells as possible into a given area, memory cell density is usually constrained by other design factors such as layout efficiency, performance, power requirements, and noise sensitivity.
In view of the trends toward compact, high-performance, high-bandwidth integrated computer networks, portable computing, and mobile communications, the aforementioned constraints can impose severe limitations upon memory structure designs, which traditional memory systems and subcomponent implementations may fail to obviate.
One type of basic storage element is the static random access memory (hereinafter referred to as “SRAM”), which retains its memory state as long as power is applied to the cell. In one embodiment of a SRAM device, the memory state is usually stored as a voltage differential within a bistable functional element, such as an inverter loop.
A SRAM cell is comparatively more complex than a counterpart dynamic RAM (hereinafter referred to as “DRAM”), requiring more constituent elements, preferably transistors. Accordingly, DRAM devices require refreshing, thus commonly consume more power and dissipate more heat than a SRAM of comparable memory density. Thus efficient lower-power SRAM device designs are particularly suitable for VLSI systems having need for high-density components, providing those memory components observe the often strict overall design constraints of the particular VLSI system.
Furthermore, the SRAM subsystems of many VLSI systems frequently are integrated relative to particular design implementations, with specific adaptations of the SRAM subsystem limiting, or even precluding, the scalability of the SRAM subsystem design. As a result SRAM memory subsystem designs, even those considered to be “scalable”, often fail to meet such design limitations once these memory subsystem designs are scaled-up for use in a VLSI system needing a greater memory cell population and/or density.
Accordingly, there is a need for an efficient, scalable, high-performance, low-power synchronous, self-timed memory structure that enables a system designer to create a SRAM memory subsystem that satisfies strict constraints of device area, power, performance, noise sensitivity, and the like.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.
SUMMARY OF THE INVENTION
One embodiment of the present invention relates to a synchronous controlled, self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local decoder interfacing with the cell array, at least one local sense amplifier and at least one local controller. The at least one local sense amplifier interfaces with at least the controller and cell array, and is adapted to precharge and equalize at least one line coupled thereto. The at least one local controller interfaces with and coordinates the activities of at least the local decoder and sense amplifier.
One embodiment of the present invention relates to a memory device. This embodiment of the memory device comprises at least a synchronous controlled global element, and a self-timed local element interfacing with the synchronous controlled global element. In one embodiment, the global element may include one or all of the following: a global predecoder; at least one global decoder; and at least one global controller. It is also contemplated that the local element may include one or all of the following: a plurality of memory cells forming at least one cell array; at least one local decoder; at least one local sense amplifier; and at least one cluster. It is further contemplated that the local elements may be broken up into blocks and sub-blocks.
Another embodiment of the present invention relates to a memory device. In this embodiment, the memory device comprises a muxing device, and at least one cluster device coupled to the muxing device, where the cluster device is adapted to sink all the local sense amps contained therein. This memory device further comprises a plurality of local clusters having a common local wordline coupling all the clusters in bloc. It is contemplated that the clusters include at least one sense amplifier adapted to be activated by a global cluster line.
A further embodiment of the present invention relates to a hierarchical memory structure that comprises a logical portion of a larger memory device. In this embodiment, the hierarchical memory structure comprises a plurality of memory cells forming at least one cell array and at least one local decoder interfacing with the at least one cell array. At least one local sense amplifier interfaces with the decoder and at least one cell array and is adapted to precharge and equalize at least one line coupled thereto. At least one local controller interfaces with and coordinates the local decoder and sense amplifier.
Yet another embodiment of the present invention relates to a sense amplifier device having at least one sense amplifier and adapted to be used in a memory device. The sense amplifier device comprises a precharging and equalizing device adapted to precharge and equalize unused lines at a predetermined value, and at least one transistor adapted to isolate the sense amplifier. In this embodiment, the sense amplifier device may include at least one PMOS transistor adapted to isolate the sense amplifier from a global bit line.
Still another embodiment of the present invention relates to a method of performing a read operation using a memory device containing at least one logical memory subsystem. Such method comprises selecting at least one cell array and at least one sub-block in the logical memory subsystem. At least one local sense amplifier is isolated and a local wordline is activated. At least one bitline in a bitline pair is discharged and a differential voltage is developed across the bitline pair. The discharge is stopped the bitline pair is equalized and precharged.
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Anvar Ali
Issa Sami
Terzioglu Esin
Winograd Gil I.
Broadcom Corporation
McAndrews Held & Malloy Ltd.
Nguyen Tan T.
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