Pulse or digital communications – Receivers – Interference or noise reduction
Reexamination Certificate
1999-10-15
2003-12-23
Chin, Stephen (Department: 2634)
Pulse or digital communications
Receivers
Interference or noise reduction
C375S355000, C704S265000, C708S313000
Reexamination Certificate
active
06668029
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed to resampling circuits and, more particularly, to digital resampling circuits capable of performing interpolation.
BACKGROUND OF THE INVENTION
In various signal processing applications, e.g. demodulation, it is desirable to obtain samples at a particular frequency, e.g., sample rate, for ease of processing.
Assuming an analog input, one way of generating the samples at the desired sample rate is to sample the analog input at the desired rate, e.g., using an analog to digital (A/D) converter. This normally involves using a crystal oscillator to control the sampling rate of the A/D converter.
Frequently, the sampling of an input signal needs to be synchronized with symbols in a received signal, e.g., a QAM signal and needs to be a multiple of the symbol rate. In the case where multiple symbol rates are to be supported, this frequently involves supporting multiple sampling rates, e.g., using different oscillators.
The processing of quadrature amplitude modulated (QAM) signals is exemplary of a case where signal sampling rate and synchronization issues arise. In the case of quadrature amplitude modulation (QAM), it is often desirable to have input samples to a demodulator at four times the symbol rate, with the sampling being synchronized with the symbols in the signal. One known way of doing this is to have a timing recovery loop that feeds back a correction signal to an external voltage-controlled crystal oscillator (VCXO) which, in turn, controls the sampling rate of an analog-to-digital (A/D) converter. This has the disadvantage of requiring analog circuitry associated with the VCXO and the timing recovery loop used to control the VCXO. In the case of demodulators that support decoding multiple symbol rates of QAM, in order for the demodulator to sample the signal at four times the symbol rate in the known manner, multiple VCXOs or a VCXO with multiple, switched crystals are required.
Generally, digital circuit implementations tend to be more reliable than analog circuit implementations. In addition, given the relatively low cost of adding digital components to integrated circuits, there continues to be a preference towards replacing analog circuit implementations with digital circuits—particularly in cases where digital circuits are being used to perform at least some functions.
In view of the above, it becomes apparent that it would be desirable to be able to sample an analog signal at one fixed rate, e.g., frequency, and then use digital signal processing to convert the resulting bitstream to a bitstream having the desired sample characteristics, e.g., a desired sample rate. It is desirable that the digital signal resampling circuits be suitable for use in a wide variety of applications including, but not limited to, demodulator circuits. It is also desirable that the circuits perform interpolation and not merely drop or repeat some of the input signals to achieved the desired output sample rate.
Accordingly, there is a need for methods and apparatus for converting a bitstream having a first sample rate into a bitstream having a second, e.g., desired sample rate. It is desirable that resampling circuits used to perform such a function be capable of being implemented as digital circuits. It is also desirable that any new resampling circuits avoid the need for multiple VCXOs and/or analog filter loops. It is also desirable that any new resampling circuits be capable of performing interpolation.
SUMMARY OF THE INVENTION
The present invention is directed to methods and apparatus for performing resampling operations. In particular, the present invention is directed to methods and apparatus for implementing digital resampling circuits which create one or more bitstreams which include samples at desired rates, from an input bitstream. The resampling circuits of the present invention achieve the desired sample rates by performing digital interpolation on samples included in an input bitstream. The interpolation is performed using a filter, e.g., an all-pass infinite impulse response filter which produces an output as a function of a controllable signal delay. As is known in the art, all-pass filters pass all frequencies input thereto.
Accordingly, through the use of digital signal processing, an input bitstream having a first sample rate can be processed to produce a bitstream having a desired second sample rate which is different from the first sample rate. This allows one or more bitstreams having different desired sample rates to be generated from an input bitstream without the use of VCXOs or analog control loops.
Thus, the digital resampling circuit of the present invention can be used to modify the sample rate of a signal. This allows demodulators and other devices requiring a desired sampling rate to generate an input bitstream using an A/D converter running off a fixed crystal oscillator, with required adjustments in the sampling rate being made by the resampling circuit of the present invention. Thus, the present invention eliminates the need for a VCXO or multiple VCXOs in a system which requires the ability to generate a signal having a desired sampling rate from an input signal.
In order to effectively resample a signal, the resampling circuit of the present invention utilizes an all-pass infinite impulse response (IIR) filter with an adjustable coefficient to effect variable delays. The variable delay IIR filter may be implemented in two stages, e.g., the first stage comprising multiple fixed delay IIR filters, and a second stage comprising an IIR filter with a finely adjustable variable delay structure. By selectively combining one of the fixed delay filters and by adjusting the second stage IIR filter delay, large adjustments in the time periods between samples can be achieved without having to implement a single variable delay structure equal to the full range of possible delays.
The digital resampling circuit of the present invention can be used in a wide range of application where a digital signal having a first sample rate needs to be processed to produce one or more digital signals having different sampling rates.
Various additional features and advantages of the present invention will be apparent from the detailed description which follows.
REFERENCES:
patent: 4989221 (1991-01-01), Qureshi et al.
patent: 5732002 (1998-03-01), Lee et al.
patent: 6226758 (2001-05-01), Gaalaas et al.
Laakso et al. (“Splitting the delay—tools for fractional delay design.” IEEE Signal Processing Mag., vol. 13, No. 1, pp. 30-60. Jan. 1996.).
Koslov Joshua L.
Lane Frank Anton
Chin Stephen
Hitachi America Ltd.
Munoz Guillermo
Straub Michael P.
Straub & Pokotylo
LandOfFree
Methods and apparatus for implementing digital resampling... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods and apparatus for implementing digital resampling..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and apparatus for implementing digital resampling... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3152444