Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate
2002-10-18
2003-11-18
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
C257S207000, C257S208000, C257S390000, C257S500000
Reexamination Certificate
active
06649945
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wiring layout to weaken an electric field generated between the lines exposed to a high voltage, particularly to the bit lines of a nonvolatile semiconductor memory.
2. Description of the Related Art
First of all, the prior art of the present invention will be explained taking a NAND flash memory, a kind of nonvolatile semiconductor memory, as an example.
FIG. 1
shows an example of a cell array of a NAND flash memory. In this example, only one NAND block (erase unit) is shown to simplify the explanation.
A NAND flash memory is a kind of electrically rewritable nonvolatile semiconductor memory. A NAND block represents an erase unit, and all the data in the memory cell of a NAND block is erased simultaneously. A NAND block has a plurality of NAND cell units
1
. These NAND cell units
1
are placed in a cell's P-well area, CPWELL, for example.
A NAND cell unit comprises a NAND string comprising a plurality of memory cells
2
connected in series, one select gate transistor
3
connected to one end of the NAND series, and another select gate transistor
3
connected to another end of the NAND series. The one select gate transistor
3
connected to the one end of the NAND series is connected to a common source line CELSRC, and the another select gate transistor
3
connected to the another end of the NAND series is connected to bit lines BL
1
e—BLne and BL
1
o—BLno.
Word lines WL
0
, WL
1
to WL
15
are connected to the memory cells
2
in the NAND cell unit, and they function as control gate electrodes of the memory cells
2
. Select gate lines SGS and SGD are connected to the select gate transistors
3
in the NAND cell unit
1
, and they function as gate electrodes of the select gate transistors
3
.
In this example, a sense amplifier (S/A)
4
employs a cell array structure with two bit lines BLie and BLio (i=1, 2, to n) connected through a select circuit
5
A. Two bit lines BLie and BLio are connected to a shielded power line BLSHIELD through a select circuit
5
B. With this structure, a so-called shielded bit line reading method can be used upon reading operation.
Namely, since the N-channel MOS transistor
6
A turns on when the control signal BLSe is “H” and the control signal BLSo is “L”, the even-numbered bit line BLie is electrically connected to the sense amplifier
4
. As the control signal BIASe becomes “L” and the control signal BIASo becomes “H” at this time, the N-channel MOS transistor
7
B is ON and the shielding potential VSHIELD (e.g., 0V) is supplied to the odd-numbered bit line BLio.
Further, since the N-channel MOS transistor
7
A turns on when the control signal BLSe is “L” and the control signal BLSO is “H”, the odd-numbered bit line BLio is electrically connected to the sense amplifier
4
. As the control signal BIASe becomes “H” and the control signal BIASo becomes “L” at this time, the N-channel MOS transistor
6
B is ON and the shielding potential VSHIELD (e.g., 0V) is supplied to the even-numbered bit line BLie.
It is noted here that the even and odd numbers are determined by the bit line numbers counted from left to right assuming the leftmost bit line to be 0.
Since all bit lines BL
1
e, . . . BLne; BL
1
o, . . . BLno become high potential (erase potential) upon erasing, the N-channel MOS transistors
6
A,
6
B and
7
A,
7
B in the select circuits
5
A and
5
B, respectively, consist of high voltage MOS transistors.
In a NAND flash memory, during writing and erasing, electric charge is injected into/ejected from the floating gate electrode by an FN tunnel current.
During the writing operation, 20V is applied to the selected word line WLj and 0V is applied to the cell's P-well area (the memory cell channel) CPWELL, for example.
During the erasing operation, 0V is applied to the word line WL
0
, WL
1
to WL
15
in the selected NAND block, and 20V is applied to the cell's P-well area (channel of memory cell) CPWELL, for example.
When erasing, all bit lines BL
1
e—BLne and BL
1
o—BLno are actually floating.
However, when 20V is applied to the cell's P-well area CPWELL, a forward bias diode (cell's P-well area+N-type diffusion layer) is connected between the cell's P-well area CPWELL and the bit lines BL
1
e—BLne and BL
1
o—BLno. As a result, the bit lines BL
1
e—BLne and BL
1
o—BLno are also charged to about 20V.
As described above, during writing or erasing, the selected word line WLj or all the bit lines BL
1
e—BLne and BL
10
—BLno are charged to about 20V. Therefore, as a potential difference between these lines and other lines increases, a dielectric breakdown occurs between these lines, and a line short-circuit problem arises.
Particularly, in recent years, the cell array has become finer and the wiring design rule has become narrower. This increases the possibility of short-circuit due to an intense electric field in and in the proximity of a cell array.
Hereinafter, the problem will be discussed in detail taking bit lines of a nonvolatile semiconductor memory, as an example.
FIG. 2
shows a wiring layout of the part indicated as the area B in FIG.
1
.
FIG. 3
shows an equivalent circuit diagram of the layout of FIG.
2
.
The bit lines BL
1
e, BL
1
o, BL
2
e, BL
2
o are arranged as metal lines M
1
with minimum width and minimum space in a memory chip.
The above-mentioned minimum width means the minimum width determined by the processing technique of lithography. The minimum space means the minimum space S
1
which is influenced by the lithography technique, but in principle makes no short-circuit in the lines due to dielectric breakdown when a voltage (potential difference) V
1
is generated between the lines.
The bit lines BL
1
e and BL
2
e are connected to the N-type drain diffusion layer of the N-channel MOS transistor
6
B through the V
1
contact plug, metal line M
0
and CS contact plug. The bit lines BL
1
o and BL
2
o are connected to the N-type drain diffusion layer of the N-channel MOS transistor
7
B through the V
1
contact plug, metal line M
0
and CS contact plug.
The shielded power line BLSHIELD is connected to the N-type source diffusion layers of N-channel MOS transistors
6
B and
7
B through a V
1
contact plug, a metal line M
0
and a CS contact plug.
The metal line M
0
means the lines in the lowest layer which are directly connected to a silicon substrate (e.g., a N-type diffusion layer) Si using a CS contact plug without passing through other metal lines. The metal line M
1
means the lines in one layer above M
0
.
The gate electrodes of the N-channel MOS transistors
6
B and
7
B are made of conductive polysilicon film containing impurities, for example.
In the wiring layout of this example, since the bit lines BL
1
e, BL
1
o, BL
2
e, BL
2
o are arranged with minimum width and minimum space, a fringe is not given to the bit lines BL
1
e, BL
1
o, BL
2
e, BL
2
o in the contact area (above the V
1
contact plug). Further, the size of the V
1
contact plug is larger than the width of the bit lines BL
1
e, BL
1
o, BL
2
e, BL
2
o.
Therefore, the space between the bit lines BL
1
e, BL
1
o, BL
2
e, BL
2
o and the V
1
contact plug becomes smaller than the minimum space where no dielectric breakdown occurs between the lines.
Specifically, in the example shown in
FIGS. 2 and 3
, the space between the bit line BL
1
o and the V
1
contact plug in the area X
1
becomes smaller than the minimum space. The space between the shielded power line BLSHIELD and the V
1
contact plug in the area X
2
is also reduced to be smaller than the minimum space.
As a result, an electric field concentrates on these reduced areas, and a dielectric breakdown occurs, spoiling the reliability of the nonvolatile semiconductor memory.
Further, in the wiring layout of this example, the bit lines BL
1
e, BL
1
o, BL
2
e, BL
2
o are arranged with minimum width and minimum space, and the space between the shielded power supply BLSHIELD and the bit lines BL
1
e, BL
1
o, BL
2
e, BL
2
o is set to be minimum.
However, it is to be n
Hosono Koji
Imamiya Kenichi
Nakamura Hiroshi
Hogan & Hartson LLP
Ngo Ngan V.
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