Pulse or digital communications – Transmitters
Reexamination Certificate
1999-06-22
2003-11-25
Fan, Chieh M. (Department: 2734)
Pulse or digital communications
Transmitters
C375S253000, C341S058000, C341S059000
Reexamination Certificate
active
06654425
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital modulation circuit, a digital modulation method, a digital demodulation circuit and a digital demodulation method. More specifically, the present invention relates to a digital modulation circuit and a digital modulation method for modulating an unknown data sequence to a recording signal waveform sequence or channel sequence to be recorded on a recording medium, and to a digital demodulation circuit and a digital demodulation method for demodulating the signal waveform sequence to a data sequence.
2. Description of the Related Art
A binary data sequence is modulated to an appropriate recording signal waveform sequence and recorded on a recording medium. For example, a binary data sequence is subjected to RLL coding and further to NRZI modulation to be recorded on the recording medium. This enhances recording density. The binary data sequence may sometimes be directly subjected to NRZ modulation or NRZI modulation to be recorded on the recording medium.
In RLL coding, datawords of m bits each are successively cut out from an input data sequence, and each dataword is translated to a codeword each of n bits. This translation has a condition for enlarging a minimum value Tmin and reducing a maximum value Tmax of a time interval between adjacent transitions of the NRZI modulated recording signal. More specifically, there is a condition that in the RLL coded code sequence, the number of bits of “0” existing between a bit “1” and another bit “1” must be at least d and at most k. The RLL code translated to satisfy the condition is referred to as (d, k; m, n) RLL code.
In NRZI modulation, an RLL code is modulated such that bit “1” is inverted and bit “0” is not inverted. Accordingly, bit inversion interval in the signal to be recorded after NRZI modulation becomes wider than the bit inversion interval in the RLL code before NRZI modulation. Therefore, as compared with when the RLL code before NRZI modulation is recorded on a recording medium and reproduced, waveform distortion in the reproduced signal can be reduced when the recording signal after NRZI modulation is recorded on the recording medium and reproduced, and as a result, error in reading can be reduced. When error in recording of approximately the same extent is tolerable, higher recording density can be attained when the recording signal after NRZI modulation is recorded on the recording medium, than when the recording signal before NRZI modulation is on the recording medium.
Desired features of the recording signal waveform sequence are as follows.
(1) Minimum value Tmin of the time interval between adjacent transition of the recording signal
Tmin is calculated as a product of “d+1” and duration of channel bit, that is, a detection widow width Tw. When recording density is made higher, inversion interval of recording signals becomes smaller, so that the reproduced signals are more susceptible to distortion because of intersymbol interference. As a result, error in reading is more likely. In order to reduce waveform distortion in reading from a recording medium with high recording density and to reduce error in recording, larger Tmin is desirable.
(2) Maximum value Tmax of the time interval between adjacent transitions of the recording signal
Tmax is calculated as a product of “k+1” and the detection window width Tw. A reproduction pulse cannot be obtained unless the polarity is inverted. Therefore, a clock cannot be directly generated from the reproduction pulse, which leads to clocks of lower accuracy. When the interval of polarity inversion becomes longer, there will be much fluctuation in DC component, and therefore smaller Tmax is desirable.
(3) DC component or constant frequency component
A recording apparatus and a reproducing apparatus have an AC coupling device. Therefore, when the recording signal has a DC component, recording signal waveform is distorted in the AC coupling device, which is not desirable. Further, it is not possible to recover in reproduction the DC component lost at the time of recording. Therefore, less DC component and less low frequency component are desired.
For evaluation of the DC component and the low frequency component in the recording signal, DSV (digital Sum Value) is used. DSV represents an accumulated value calculated from the start point of the waveform sequence of the recording signal, with the value of bit “1” regarded as “+1” and the value of bit “0” as “−1”. If the absolute value of DSV is small, it means that the DC component or the low frequency component is small. For evaluation of the DC component and the low frequency component of each code, CDS (Codeward Digital Sum) is used. CDS represents DSV in each codeword, and smaller CDS represents smaller DC component or low frequency component of the corresponding codeword.
(4) Detection window width Tw
Detection window width Tw is given by (m
)T, which represents a time which can be used for detection of a reproduction bit, that is, resolution. Further, the detection window width Tw represents window margin against phase fluctuation of the reproduced signal caused by waveform or intersymbol interference or noise, and larger value is desirable.
(5) Constraint length Lc.
In order to improve Tmin, Tmax and DSV, sometimes coding is performed with reference to preceding and succeeding codewords. The length of the preceding or succeeding codeword referred to at that time is called constraint length Lc. As Lc becomes larger, error propagation becomes larger and circuit configuration becomes more complicated. Therefore, smaller Lc is desired.
Japanese Patent Laying-Open No. 52-128024 discloses a technique for marking Tmin larger and marking Tmax smaller in the recording signal after NRZI modulation. According to this Laid-Open application, by RLL coding in which datawords each of 2 bits are successively cut out from an input data sequence and translated to codewords each of 3 bits, (
1
,
7
;
2
,
3
) RLL codes are produced. Code sequences of thus produced RLL code are subjected to NRZI modulation. When the condition of d=1 cannot be satisfied, (
1
,
7
;
4
,
6
) RLL codes are produced.
Japanese Patent Publication No. 1-27510 discloses a technique of coding (RLL coding) for reducing DC component of the recording signal after NRZI modulation is disclosed, in which coding is performed so as not to reduce Tmin of the recording signal after NRZI modulation. According to this published application, blocks each of n bits are successively cut out from a code sequence after coding, and between adjacent blocks, redundancy bits each consisting of a plurality of bits are inserted. The code sequence with redundancy bits inserted is supplied to an NRZI modulation circuit. Here, redundancy bits are selected dependent on whether code inversion is necessary between the blocks to which the redundancy bits are to be inserted, and on the state of the last part of the immediately preceding block. More specifically, the redundancy bits are selected so as to reduce DC component of the NRZI modulated recording signal and not to reduce Tmin.
Further, Japanese Patent Publication No. 5-34747 discloses a coding scheme in which rule of translation, i.e. a look-up table for translating a data sequence to RLL codes is adjusted in accordance with arrangement of data sequence, whereby Tmin of 1.5T, Tmax of 4.5T and Lc of 5T can be attained.
Japanese Patent Publication No. 4-77991 discloses a technique for reducing DC component of the recording signal after NRZI modulation and to enlarge Tmin. According to this published application, datawords each of 8 bits are successively cut out from an input data sequence, and each dataword is translated to codewords each of 14 bits. Translation is performed such that in the translated code sequence, the number of bits of “0” is at least 1 and at most 8 between a bit “1” and another bit “1”. There are two tables prepared for translating a dataword of 8 bits to a codeword of 14 bits, and dependent on the
Itoh Nobuo
Kunisa Akiomi
Takahashi Seiichiro
Armstrong Westerman & Hattori, LLP
Fan Chieh M.
Sanyo Electric Co,. Ltd.
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