Spare memory arrangement

Details Spare memory arrangement Spare memory arrangement

1990-12-04

1994-01-04

Dixon, Joseph L.

G06F 1216, G06F 1202

Patent

active

052768341

ABSTRACT:
A spare memory arrangement in which a defective chip in a memory array can be electronically replaced with a spare chip of identical construction. A defective memory chip is first detected and located by a suitable means, such as an error correction code (ECC), check sum, or parity check. A sparer chip is constructed to be actuated upon a read to the defective memory chip to replace the defective chip with a memory spare chip. The sparer chip includes a cross-point memory (CPM) cell having an address register for receiving data from a central processing unit (CPU) and routing the data to and from the spare memory chip. The cross-point memory (CPM) cell is actuated by control input from the (CPU).

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