Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1998-06-01
2003-10-14
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S751000, C257S758000, C257S759000, C257S760000, C257S914000
Reexamination Certificate
active
06633082
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device and method for manufacturing the semiconductor device. More particularly, the invention relates to a semiconductor device which has a multilayer wiring structure and uses a film having a low dielectric constant as an interlayer insulating film and relates to a method for manufacturing the semiconductor device.
BACKGROUND OF THE INVENTION
As the density of the large scale integration of semiconductor devices has increased, the density of the multilayer wiring structure of the semiconductor devices has also increased. With the increased density of the wiring structure, the wirings adjacent to each other on the same layer and the wirings adjacent to each other on different layers still must be well insulated by an interlayer insulating film.
FIG. 10
shows a sectional view of a semiconductor device having a multilayer wiring structure. Such device is described in Japanese published unexamined patent application No. H8-107149. As shown in the figure, the device contains a semiconductor substrate
101
and an element separating area
102
provided on the semiconductor substrate
101
. A diffusion layer area
103
is formed in the semiconductor substrate
101
in an area of the substrate
101
that is partitioned by the element separating area
102
.
A metal oxide semiconductor (“MOS”) transistor is formed on the diffusion layer area
103
of the semiconductor substrate
101
and contains source and drain areas
121
, a gate oxide film
122
, a gate electrode
123
, and side wall oxide films
124
. A first interlayer insulating film
104
is provided over the element separating area
102
and the diffusion layer area
103
, and contact openings
105
are selectively formed in the first interlayer insulating film
104
. The inner walls of the contact openings
105
are lined with a barrier metal
106
, and the contact openings
105
are filled with tungsten
107
which extends to the upper surface of the first interlayer insulating film
104
.
Then, a first wiring layer
108
containing mainly aluminum is formed on the first interlayer insulating film
104
at least in an area above the contact openings
105
. A first oxide film
109
is formed over the first wiring layer
108
by a plasma chemical vapor deposition (“CVD”) process such that the upper and side surfaces of the first wiring layer
108
are covered. Also, the portion of the first oxide film
109
on the side surface of the first wiring layer
108
is thinner than the portion of the first oxide film
109
on the upper surface of the first wiring layer
108
. For example, if the portion of the first oxide film
109
on the upper surface has a thickness of 100 nm, the portion of the film
109
on the side surface has a thickness of approximately 50 nm.
Also, a hydrogen silsesquioxane (“HSQ”) layer
110
is used as a film having a low dielectric constant and is formed over the first oxide film
109
, and a second oxide film
111
is formed on the upper surface of the HSQ layer
110
. Then, the upper surface of the second oxide film
111
is flattened. Since the portion of the first oxide film
109
on the side surface of the first wiring layer
108
is thin in comparison to the portion of the film
109
on the upper surface, the space in which the HSQ layer
110
(i.e. the film with the low dielectric constant) is provided between the wirings of the first wiring layer
108
is increased. Therefore, the spacing between adjacent wirings can be reduced. Also, instead of using the HSQ layer
110
as the film with a low dielectric constant, a layer of parylene, benzocyclobutene (“BCB”), or other material may be used.
A via hole
112
is selectively formed in the first oxide film
109
, the HSQ layer
110
, and the second oxide film
111
, and the inner wall of the via hole
112
is lined with a barrier metal
113
which extends to the upper surface of the second oxide film
111
. Then, the via hole
112
is filled with tungsten
114
. A second wiring layer
115
containing an aluminum alloy is formed on the second oxide film
111
at least in an area above the via hole
112
. A cover film
116
consisting of plasma SiON which is 1 &mgr;m thick is formed on the second wiring layer
115
.
The method in which the semiconductor device shown in
FIG. 10
is manufactured will be described below in conjunction with
FIGS. 11A
,
11
B, and
12
. As shown in
FIG. 11A
, the element separating area
102
is formed on the semiconductor substrate
101
by a LOCOS method and other methods, and the diffusion layer area
103
is formed via ion implantation in an area of the semiconductor substrate
101
defined by the element separating area
102
. The source and drain areas
121
are formed in the diffusion layer area
103
, and the gate oxide film
122
, the gate electrode
123
, and the side wall oxide films
124
of the MOS transistor are formed on the diffusion layer area
103
.
The first interlayer insulating film
104
is formed over the element separating area
102
, the diffusion layer area
103
, and the MOS transistor. Also, the first interlayer insulating film
104
contains an oxide film layer which is approximately 100 nm thick and a boron phospho silicate glass (“BPSG”) layer which is approximately 700 nm thick and which is formed on the oxide film layer. The contact openings
105
are selectively formed over the source and drain areas
121
of the MOS transistor, and the barrier metal
106
is formed on the inner surface of the contact openings
105
. Then, the contact openings
105
are filled with tungsten
107
via a CVD process, and the first wiring layer
108
containing an aluminum alloy is formed over at least the contact openings
105
via a patterning process. The first wiring layer
108
has a thickness of 0.4 &mgr;m, and the distance between adjacent wirings of the first wiring layer
108
is approximately 0.3 &mgr;m.
As shown in
FIG. 11B
, the first oxide film
109
is formed over the first interlayer insulating film
104
and the first wiring layer
108
via a plasma CVD process such that it is approximately 50 nm thick on the upper surface of the first wiring layer
108
. The HSQ layer
110
is formed by a spin coating method so that it is approximately 400 nm thick in the flat part. In other words, the thickness of the portion of the HSQ layer
110
which is not directly over the wiring layer
108
is approximately 400 nm. Afterwards, the HSQ layer
110
is baked at a temperature of approximately 350° C. Then, a heat treatment is applied to the layer
110
at approximately 400° C. to eliminate an organic component such as isomethylbutyl ketone which functions as a solvent.
Then, as shown in
FIG. 12
, the second oxide film
111
is formed over the HSQ layer
110
and is approximately 2 &mgr;m thick. Afterwards, the second oxide film
111
is flattened by a chemical mechanical polishing (“CMP”) process and other processes. The via hole
112
is selectively made through the is first oxide film
109
, the HSQ layer
110
, and the second oxide film
111
, and the barrier metal
113
containing titanium nitride is formed on the inner surface of the via hole
112
. Then, the via hole
112
is filled with tungsten
114
formed by a blanket CVD process, and an etchback process is performed. Afterwards, the second wiring layer
115
containing an aluminum alloy is formed via a patterning process and has a thickness of 0.4 &mgr;m. Then, the semiconductor device is completed by forming the cover film
116
containing plasma SiON on the second wiring layer
115
at a thickness of approximately 1 &mgr;m.
In the semiconductor device described above, the first oxide film
109
formed on the side wall of the first wiring layer
108
is thinned in order to enhance the effect achieved by the HSQ layer
110
having a low dielectric constant. However, since the first oxide film
109
is thinned, moisture in the HSQ layer
110
can penetrate the first oxide layer
109
. As a result, the moisture increases the current which leaks between the adjacent wirin
Matsumoto Akira
Oda Noriaki
NEC Corporation
Rao Shrinivas H.
Sughrue & Mion, PLLC
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