Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
2003-01-06
2003-11-25
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
Reexamination Certificate
active
06653656
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a semiconductor device and a method of manufacturing the same, and in particular to a semiconductor device formed on an insulating layer and a method of manufacturing the same.
2. Description of the Background Art
In order to improve the performance of semiconductor devices, there have been developed semiconductor devices in which circuit elements are isolated by dielectrics and a floating capacitance is small. For forming transistors on a thin silicon film on an insulating film, which will be referred to as an SOI (Silicon On Insulation) layer, an MESA isolating method is used for isolating the transistors from each other. According to this MESA isolating method, the isolated transistors are formed at completely isolated or insular SOI layers, respectively. This brings about many advantages such as prevention of influence of latch-up between adjacent transistors.
FIGS. 198
to
206
are cross sections showing a process of manufacturing an SOI-MOSFET using a conventional MESA isolating method. Referring to
FIG. 206
, description will be given on a structure of the SOI-MOSFET formed by the conventional MESA solating method. In this SOI-MOSFET, a buried oxide film
2
is formed on a silicon substrate
1
. SOI layers
3
are formed at predetermined regions on buried oxide film
2
with a predetermined space between each other. Silicon substrate
1
, buried oxide film
2
and SOI layers
3
form an SOI substrate. Source/drain regions
3
e
and
3
f
having an LDD structure are formed on SOI layer
3
at an PMOS region with a predetermined space between each other and are located at opposite sides of a channel region
3
g
. Titanium silicide films
8
a
are formed on the surfaces of source/drain regions
3
e
and
3
f
. A gate electrode
6
is formed on channel region
3
g
with a gate oxide film
5
therebetween. Titanium silicide film
8
a
is also formed also on the upper surface of gate electrode
6
. Side wall oxide films
13
are formed in contact with side surfaces of gate electrode
6
.
On SOI layer
3
at an NMOS region, there are formed source/drain regions
3
b
and
3
c
having an LDD structure with a predetermined space between each other and are located at opposite sides of a channel region
3
d
. A gate electrode
6
is formed on channel region
3
d
with a gate oxide film
50
therebetween. Side wall oxide films
13
are formed in contact with side surfaces of gate electrode
6
. Titanium silicide films
8
a
are formed on source/drain regions
3
b
and
3
c
and gate electrode
6
. The PMOS and NMOS regions are covered with an interlayer oxide film
9
. Contact holes are formed at regions of interlayer oxide film
9
located above source/drain regions
3
b
,
3
c
,
3
e
and
3
f
. There are provided metal interconnection layers
10
having portions filling the contact holes. Gate electrodes
6
are formed of polycrystalline silicon films containing phosphorus (P) at 1×10
20
/cm
2
or more. Titanium silicide films
8
a
are formed for reducing resistances of source/drain regions
3
b
,
3
c
,
3
e
and
3
f
and gate electrode
6
.
Referring to
FIGS. 198
to
206
, a process of manufacturing the SOI-MOSFET using the conventional MESA isolating method will be described below.
As shown in
FIG. 198
, buried oxide film
2
is first formed on silicon substrate
1
. After forming SOI layer
3
on buried oxide film
2
, a surface of SOI layer
3
is oxidized to form oxide film
5
having a thickness from about 100 Å to about 200 Å. A resist
201
is formed at predetermined regions on oxide film
5
. Using resist
201
as a mask, dry etching is effected on oxide film
5
and SOI layer
3
. Thereby, SOI layers
3
forming active regions of transistors spaced by a predetermined distance are formed as shown in FIG.
199
.
In this isolating method, predetermined regions of SOI layer
3
are removed by the etching to break electrical connection between adjacent transistors, which is called the MESA isolating method. Thereafter, resist
201
is removed. A resist
202
is formed to cover the PMOS region. Using resist
202
as a mask, boron ions are implanted into SOI layer
3
at the NMOS region under the conditions of 20 keV and 1×10
12
-3×10
12
/cm
2
. This implantation is performed for forming the channel region of NMOSFET. Thereafter, resist
202
is removed.
As shown in
FIG. 200
, a resist
203
is then formed over the NMOS region. Using resist
203
as a mask, phosphorus ions are implanted into SOI layer
3
at the PMOS region under the conditions of 30 kev and 1×10
11
-3×10
11
/cm
2
. This implantation is performed for forming the channel region of the PMOSFET. Thereafter, resist
203
is removed. Oxide film
5
on SOI layer
3
is removed.
As shown in
FIG. 201
, gate oxide film
50
having a thickness of about 100 Å is formed over each SOI layer
3
. Polycrystalline silicon layer
6
containing phosphorus at 1×10
20
/cm
2
or more and having a thickness of about 2000 Å is formed over gate oxide films
50
and buried oxide film
2
. A resist
204
is formed at predetermined regions on polycrystalline silicon layer
6
. Using resist
204
as a mask, dry etching is effected on polycrystalline silicon layer
6
to form gate electrodes
6
as shown in FIG.
202
. After removing resist
204
(shown in FIG.
201
), a resist
205
is formed over the PMOS region. Using resist
205
and gate electrodes
6
at the NMOS region as a mask, phosphorus ions are implanted into SOI layer
3
at the NMOS region under the conditions of 40 keV and 1×10
13
-3×10
13
/cm
2
. This implantation is performed for forming a lightly doped region in the LDD structure. Thereafter, resist
205
is removed.
As shown in
FIG. 203
, a resist
206
is formed over the NMOS region. Using resist
206
as a mask, boron ions are implanted into SOI layer
3
at the PMOS region under the conditions of 20 keV and 1×10
13
-3×10
13
/cm
2
. This implantation is performed for forming a lightly doped region forming the LDD structure of the PMOSFET. Thereafter, resist
206
is removed.
As shown in
FIG. 204
, side wall insulating films
13
are formed in contact with side surfaces of gate electrode
6
. Side wall insulating films
13
may be formed by effecting anisotropic etching on an insulating film (now shown) which was formed over gate electrode
6
. Thereafter, a resist
207
is formed over the PMOS region. Using resist
207
, gate electrode
6
at the NMOS region and side wall insulating films
13
as a mask, phosphorus ions are implanted into SOI layer
3
at the NMOS region under the conditions of 40 keV and 4×10
15
-6×10
15
/cm
2
. This implantation is performed for forming heavily doped regions forming the source/drain regions in the NMOSFET. Thereafter, resist
207
is removed. Arsenic may be used as implanted ion species for the source/drain regions.
As shown in
FIG. 205
, a resist
208
is formed over the NMOS region. Using resist
208
, gate electrode
6
at the PMOS region and side wall insulating films
13
as a mask, boron ions are implanted into SOI layer
3
at the PMOS region under the conditions of 20 keV and 4×10
15
-6×10
15
/cm
2
. This implantation is performed for forming heavily doped regions forming the source/drain regions in the PMOSFET. Thereby, source/drain regions
3
e
and
3
f
having the LDD structure are formed. Thereafter, resist
208
is removed.
Then, as shown in
FIG. 206
, titanium silicide layers
8
a
are formed on the surfaces of source/drain regions
3
b
,
3
c
,
3
e
and
3
f
and gate electrodes
6
. After forming interlayer insulating film
9
of about 7000 Å in thickness over the whole surface, the contact holes are formed at regions located above source/drain regions
3
b
,
3
c
,
3
e
and
3
f
. The aluminum layer having portions filling the contact holes is formed and then is patterned to form metal interconnection layers
10
. In this manner, the SOI-C
Furukawa Akihiko
Inoue Yasuo
Iwamatsu Toshiaki
Maeda Shigenobu
Miyamoto Shoichi
McDermott & Will & Emery
Meier Stephen D.
Mitsubishi Denki & Kabushiki Kaisha
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