System with enhanced execution of address-conflicting instructio

Details System with enhanced execution of address-conflicting instructio System with enhanced execution of address-conflicting instructio

1990-11-14

1994-01-04

Harrell, Robert B.

Boots, shoes, and leggings

3642318, 364263, 3642631, 3642632, 3642624, 3642716, 364DIG1, G06F 938, G06F 926, G06F 928

Patent

active

052768228

ABSTRACT:
An information processor includes an immediate data latch and a pair of multiplexers in an input portion of an adder in a data address generator. The structure controls operation of the multiplexer in accordance with a register conflict detecting control signal and eliminates an idle state of a pipeline by detecting a register conflict between a register for holding immediate data, indicated by a precedent instruction instructing a specific register to store the immediate data, and a register used for calculation of memory addresses to be used for execution of a succeeding load/store instruction. The immediate data latch directly latches an immediate data indicated by the precedent instruction and outputted by an instruction decoding portion. Then, if the register conflict detecting portion detects the register conflict, the immediate data latched by the immediate data latch is used for calculation of memory addresses. This control operation is performed by changing the multiplexer according to the register conflict control signal to input the data from the immediate data latch to the adder.

REFERENCES:
patent: 4916606 (1990-04-01), Yamaoka et al.
patent: 5075849 (1991-12-01), Kuriyama et al.
patent: 5127093 (1992-06-01), Moore, Jr.
patent: 5136696 (1992-08-01), Beckwith et al.
patent: 5179697 (1993-01-01), Nishii et al.

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