Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated...
Reexamination Certificate
2001-07-02
2003-12-23
Everhart, Caridad (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
C257S758000, C257S772000, C257S396000, C257S397000, C257S751000, C257S752000
Reexamination Certificate
active
06667530
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more specifically to a semiconductor device having a multi-layer interconnection structure for use in an integrated circuit, and a manufacturing method thereof.
2. Description of the Background Art
FIG.
23
and
FIGS. 24
to
30
are schematic cross-sectional views that show the structure of a conventional semiconductor device having a multi-layer interconnection structure and a manufacturing method thereof, which are described, for example, on page 30 in “Electronic Journal”, December Issue, 1997.
Referring to
FIG. 23
, an etching stopper layer
115
made of, for example, SiN film (silicon nitride film) is formed on a lower-layer interconnection
114
. On the etching stopper layer
115
, an interlayer film
101
made of, for example, SiO
2
film (silicon oxide film) is formed. On the upper surface of the interlayer film
101
, a groove
102
a
that for filling with interconnection and a connection hole
101
a
that reaches the lower-layer interconnection
114
from the bottom surface of the groove
102
a
are formed.
A barrier metal
103
made of, for example, TaN (tantalum nitride) film is formed along the inner surface of the connection hole
101
a
and the groove
102
a
, and a Cu film
104
is formed so as to be embedded in the connection hole
101
a
and the groove
102
a
. The barrier metal
103
and the Cu film
104
constitute an upper interconnection.
Next, an explanation will be given of the manufacturing method of the conventional semiconductor device shown in FIG.
23
.
Referring to
FIG. 24
, the etching stopper layer
115
and the interlayer film
101
are successively formed on the lower-layer interconnection
114
by a plasma CVD (Chemical Vapor Deposition) method.
Referring to
FIG. 25
, after photoresist has been applied to the interlayer film
101
, this is exposed and developed to form a resist pattern
121
a
having a pattern of connection holes.
Referring to
FIG. 26
, the interlayer film
101
is subjected to a dry etching process using this resist pattern
121
a
as a mask. Thus, a hole
101
a
that reaches the etching stopper layer
115
is formed in the interlayer film
101
. Thereafter, the resist pattern
121
a
is removed by ashing and a chemical treatment.
Referring to
FIG. 27
, after photoresist has been applied to the interlayer film
101
, this is exposed and developed to form a resist pattern
121
b
having a pattern of grooves.
Referring to
FIG. 28
, the interlayer film
101
is subjected to a dry etching process using this resist pattern
121
b
as a mask to form a groove
102
a
used for interconnection in the interlayer film
101
. Thereafter, the resist pattern
121
b
is removed by ashing and a chemical treatment.
Referring to
FIG. 29
, the etching stopper layer
115
exposed from the hole
101
a
is removed by the dry etching process so that one portion of the surface of the lower-layer interconnection
114
is exposed.
Referring to
FIG. 30
, a barrier metal
103
and a seed layer for a plating film are formed on the interlayer film
101
. With respect to the barrier metal, a TaN film is used, and a Cu film is used as the seed layer. The TaN film
30
is formed with a thickness of 20 nm by, for example, a sputtering method, and the Cu film forming the seed layer is formed with a thickness of 200 nm by, for example, a sputtering method. Thereafter, Cu is deposited by an electrolytic plating method in a manner so as to fill the groove
102
a
and the connection hole
101
a
, thereby forming a Cu film
104
.
Then, the Cu film
104
and the barrier metal
103
are abraded and removed by a chemical mechanical polishing method (CMP method) until the upper surface of the interlayer film
101
has been exposed, and allowed to remain only in the connection hole
101
a
and the groove
102
a
so as to form interconnection. The above-mentioned processes are repeated to form multi-layer interconnection.
Since the conventional semiconductor device having a multi-layer interconnection structure is designed as described above, the depth of etching of the hole
101
a
has a value that corresponds to the sum of the depth of the connection hole and the height of the interconnection, as illustrated in FIG.
26
. For this reason, upon forming the hole
101
a
, an extremely deep etching process is required, and this etching has to be stopped by the thin etching stopper layer
115
. Consequently, it is very difficult to carry out etching on the hole
101
a
, with the result that, due to a reduction in the margin of safety of the process, problems arise in which the etching finishes before the connection hole
101
a
has been completely opened, causing an insufficient opening or, in contrast, penetration occurs in the etching layer
115
.
The insufficient opening causes insufficient connection in the connection hole
101
a
. Moreover, the penetration of the etching stopper layer
115
causes surface oxidation of the lower-layer interconnection
114
, resulting in an increase in the connection resistance and insufficient connection. These problems have caused a problem of an extreme reduction in the yield of the multi-layer interconnection.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device having a multi-layer structure and a manufacturing method thereof, which is possible to form a connection hole and a groove by using a simple process, and consequently to improve the yield as well as to reduce the number of processes and the production costs.
According to the present invention, there is provided a semiconductor device having a multi-layer interconnection structure in which a lower-layer interconnection and an upper-layer interconnection are laminated with an insulating film interpolated in between, wherein the insulating film has a groove filled with the upper layer interconnection on its upper surface, a connection hole for connecting the upper-layer interconnection and the lower-layer interconnection, and a photosensitive film.
In accordance with the semiconductor device of the present invention, the insulating film has a photosensitive property; therefore, after the insulating film has been exposed, this is developed so that a groove and a connection hole are formed. In this developing process, since only the photosensitive insulating film can be selectively removed, it is possible to prevent penetration through the stopper layer located beneath the photosensitive insulating film. Therefore, since the developing time and other conditions can be set without the need of taking the penetration of the stopper layer into consideration, it is possible to effectively prevent the insufficient opening. Consequently, it becomes possible to improve the yield and also to reduce the number of processes and the production costs.
Here, the photosensitive insulating film of the present invention refers to an insulating film whose solubility to a developing solution changes from a soluble state to an insoluble state or from an insoluble state to a soluble state, upon irradiation with light or energy particles.
In the above-mentioned semiconductor device, the insulating film preferably provided has a structure in which a lower-layer insulating film and an upper-layer insulating film that are exposed to mutually different wavelengths are laminated, and a connection hole is formed in the lower-layer insulating film and a groove is formed on the upper-layer insulating film.
With this arrangement, the connection hole and the groove are formed in a separate manner by changing only the wavelength of exposure light.
In the above-mentioned semiconductor device, the wavelength to which the lower-layer insulating film is exposed is set to be shorter than the wavelength to which the upper-layer insulating film is exposed.
With this arrangement, it becomes possible to form the connection hole and the groove by using fewer processes.
In the above-mentioned semiconductor device, the in
Everhart Caridad
Leydig , Voit & Mayer, Ltd.
Mitsubishi Denki & Kabushiki Kaisha
Yevisikow V.
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