Method for manufacturing annealed wafer and annealed wafer

Details Method for manufacturing annealed wafer and annealed wafer Method for manufacturing annealed wafer and annealed wafer

2002-08-05

2003-11-11

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

Thinning of semiconductor substrate

C438S308000, C438S463000, C438S509000, C438S798000, C438S799000

Reexamination Certificate

active

06645834

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a manufacturing process for an annealed wafer obtained by heat-treating a silicon mirror wafer, and an annealed wafer.
BACKGROUND ART
In order to acquire an excellent oxide film dielectric breakdown strength characteristic, there has been adopted a method wherein a silicon wafer is subjected to high temperature hydrogen (H
2
) annealing or high temperature argon (Ar) annealing. These high temperature annealed wafers, however, have been known to be inferior to an ordinary mirror finished wafer (a mirror wafer) in a surface roughness index named haze.
This is because silicon atoms on a surface of a silicon wafer are rearranged so as to assume a lower surface energy state in high temperature annealing thereof, leading to irregularities named atomic steps stepwise generated on the surface as a result of sensitive reflection of a crystallographic orientation of the surface. The haze degrades a device characteristic; therefore a silicon wafer with a lower haze value is more highly evaluated in terms of quality. Such an inclination is said to become more explicit with smaller minimum dimensions of design rules and a smaller thickness of a gate oxide film.
As a method for reducing haze on such an annealed wafer, a technique is disclosed in JP A 93-152179 in which a silicon wafer with a sliced surface tilted from a silicon (100) plane by an angle of 0.2 to 2.0 degrees is annealed in a reductive gas atmosphere.
On the other hand, another technique of the kind is disclosed in JP A 96-321443, in which a semiconductor wafer having a vicinal (100) surface with a tilt angle of 0.1 degree or less is heat treated in a atmosphere including at least one of H
2
gas and Ar gas at a prescribed temperature for a prescribed time.
The above described JP A 93-152179 has a main feature that since a silicon wafer shows haze in rainbow colors on a surface thereof when the silicon wafer with a tilt angle of 0.2 degree or less from a silicon (100) plane is annealed in the reductive atmosphere, the tilt angle from the silicon (100) plane before the annealing is set to the range of from 0.2 to 2.0 degrees.
On the other hand, in the above described JP A 96-321443, it is described that occurrence of haze in annealing is suppressed with a tilt angle from a (100) plane of being 0.1 degree or less.
That is, it is found that there has been a conflicting ambivalence between main features of the prior art techniques, concerning a relationship between a tilt angle from a (100) plane of a wafer to be annealed and haze generated on a surface thereof by the annealing.
DISCLOSURE OF THE INVENTION
It is accordingly an object of the present invention to provide a manufacturing process for an annealed wafer capable of elucidating a relationship between a tilt angle from a (100) plane of a wafer to be annealed and haze to set optimal tilt angles for suppression of haze and to improve a characteristic of a device as a result of the suppression of haze.
In order to achieve the above object, a manufacturing process for an annealed wafer of the present invention comprises the steps of: preparing a silicon mirror wafer having a surface orientation with a tilt angle (an off angle) &thgr; in the range of 0.1 degree <&thgr;<0.2 degree from a (100) plane or a plane equivalent thereto; and heat-treating the silicon mirror wafer in an atmosphere of hydrogen gas, an inert gas, nitrogen gas or a mixed gas thereof.
The silicon mirror wafer can be manufactured from a wafer prepared by slicing a silicon single crystal ingot so as to cause a tilt angle &thgr; of a slicing plane to fall in the range of 0.1 degree <&thgr;<0.2 degree from a (100) plane or a plane equivalent thereto.
An annealed wafer manufactured by such a manufacturing process has a surface orientation with a tilt angle &thgr; in the range of 0.1 degree <&thgr;<0.2 degree from a (100) plane or a plane equivalent thereto, a low haze level and a high oxide film dielectric breakdown strength.
The inventors of the present invention have conducted a detailed research on a relationship between a tilt angle from a (100) plane of a wafer to be annealed and haze; as a result, obtained novel findings that a haze level varies largely depending on the change in observation mode for haze (a spatial frequency in measurement) from Experimental Examples 1 and 2 described later, which has lead to completion of the invention.


REFERENCES:
patent: 5534294 (1996-07-01), Kubota et al.
patent: 5966625 (1999-10-01), Zhong et al.
patent: 6294469 (2001-09-01), Kulkarni et al.
patent: 2003/0008478 (2003-01-01), Abe et al.
patent: 2172233 (2001-01-01), None
patent: H05-152179 (1993-06-01), None
patent: H05-347256 (1993-12-01), None
patent: H08-264401 (1996-10-01), None
patent: H08-264402 (1996-10-01), None
patent: H08-264780 (1996-10-01), None
patent: H08-321443 (1996-12-01), None
patent: H11-121407 (1999-04-01), None
International Patent Search dated Jan. 15, 2002.

Affiliated with

Also associated with

Rating

Method for manufacturing annealed wafer and annealed wafer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacturing annealed wafer and annealed wafer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing annealed wafer and annealed wafer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3146093