Demodulator synchronization loop lock-in detection circuit

Details Demodulator synchronization loop lock-in detection circuit Demodulator synchronization loop lock-in detection circuit

1999-06-15

2003-10-28

Deppe, Betsy L. (Department: 2734)

Pulse or digital communications

Receivers

Angle modulation

C375S373000, C329S304000

Reexamination Certificate

active

06639952

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a demodulator, and more specifically to a QPSK demodulator for demodulating a signal that simultaneously transmits two binary signals over two carriers of the same frequency but in phase quadrature.
2. Description of Related Art
A Quadrature Phase-Shift Keying (QPSK) demodulator is used to demodulate a signal that simultaneously transmits two binary signals over two carriers of the same frequency but in phase quadrature. The QPSK demodulator both restores the binary signal pair as it was transmitted and extracts the binary values from the pair of reconstructed signals. The present invention is concerned with the extraction of the binary values from the reconstructed signals, and more specifically with detecting the synchronization of the internal clock on the binary signal transmission rate.
FIG. 1
shows the portion of a conventional QPSK demodulator that extracts the binary values from the reconstructed signals. As shown, two analog-to-digital (A/D) converters
10
receive two analog signals Ia and Qa that correspond to the pair of binary signals I and Q after a rough demodulation.
The A/D converters
10
are controlled by a clock signal SCK with a frequency that is greater than the transmission rate of the binary values by the signals I and Q. The outputs of the analog-to-digital converters
10
are supplied to an interpolation filter
12
. Based on the sample pairs provided by the A/D converters
10
, the interpolation filter
12
calculates the values Is and Qs corresponding to each transmitted binary value pair. The selection of samples Is and Qs is determined by a restored clock CKR that is synchronized on the binary value transmission. In general, the edges of the restored clock CKR, which determine the samples to be selected, occur between two successive samples.
The position of an edge of the restored clock CKR between two samples is indicated by a coefficient k that is used by the filter
12
to interpolate the value of the sample to be selected. This measure is necessary, especially when the binary value transmission rate is close to the sampling frequency of the A/D converters
10
, because the restoration of the clock signal CKR is dependent on the amplitude variations of the selected samples. The restored clock CKR and the coefficient k are provided by a digitally controlled oscillator
14
that receives a frequency set point from a synchronization error detection circuit
16
via a low-pass filter
18
. The error detection circuit
16
calculates a digital error value based on binary values Is and Qs from the interpolation filter
12
through one of the many conventional error calculation algorithms.
The synchronization loop formed of elements
12
,
14
,
16
, and
18
synchronizes the clock CKR on the binary value transmission. Because these binary values are provided through a rough demodulation, the carrier has not been totally suppressed from the transmitted signals and the vector of components Is and Qs rotates at a frequency equal to the demodulation frequency error. This error is suppressed by a rotation correction circuit that is typically placed (as shown in dotted lines) between the filter
12
and the error detection circuit
16
, but can also be placed further downstream.
One problem that arises in such a QPSK demodulator is that the binary value transmission rate can vary widely, and the synchronization loop is generally incapable of re-synchronizing after a change in the transmission rate. To achieve synchronization, successive frequency tests are generally performed and a lock-in detector is used to indicate when the right frequency has been found. A first type of conventional lock-in detector uses the synchronization error signal from the error detection circuit
16
and indicates a lock-in when the error falls below a threshold. However, when receiving conditions are poor, there is no significant difference between the error signals for a locked-in system and an “unlocked” system.
To overcome this problem, another type of lock-in detector uses an algorithm to analyze the stability of the instantaneous frequency. However, such an analysis itself has poor reliability and requires confirmation through many cross-checks, which makes the process particularly complex and slow.
SUMMARY OF THE INVENTION
In view of these drawbacks, it is an object of the present invention to overcome the above-mentioned drawbacks and to provide a lock-in detection circuit with a fast response time. To detect the lock-in of a loop that synchronizes an internal clock on the transmission of values, the module of each vector that has as components the two values of each pair is calculated and compared with a stored threshold. The lock-in condition is determined according to the ratio of the number of modules greater than or smaller than the threshold to the total number of modules.
Another object of the present invention is to provide a lock-in detection circuit that is reliable under poor receiving conditions.
One embodiment of the present invention provides a method for detecting the lock-in of a loop that synchronizes an internal clock on the transmission of value pairs provided by a demodulator. According to the method, a module of a vector that has as components the values of one of the value pairs is calculated, and the module is compared with a threshold that is smaller than a theoretical module. The locked-in condition is determined according to the ratio of the number of modules found to be greater than or smaller than the threshold to the total number of modules. In one preferred method, the threshold is incremented by a first value if the module is greater than the threshold and is decremented by a second value if the module is less than the threshold.
Another embodiment of the present invention provides a lock-in detection circuit for detecting the lock-in of a loop that synchronizes an internal clock on the transmission of value pairs provided by a demodulator. The lock-in detection circuit includes a calculation circuit, a register, a comparator, a modification circuit, and an analysis circuit. The calculation circuit calculates a module of a vector that has as components the values of one of the value pairs. The register stores a threshold and the comparator compares the stored threshold with the calculated module. The modification circuit modifies the stored threshold based on the comparison result, and the analysis circuit analyzes the stored threshold to determine the locked-in condition. In a preferred embodiment, the modification circuit increments the stored threshold by a first value if the module is greater than the stored threshold, and decrements the stored threshold by a second value if the module is smaller than the stored threshold.


REFERENCES:
patent: 4712221 (1987-12-01), Pearce et al.
patent: 4987375 (1991-01-01), Wu et al.
patent: 5425057 (1995-06-01), Paff
patent: 5694440 (1997-12-01), Kallman et al.
patent: 5703526 (1997-12-01), Meyer
patent: 5861773 (1999-01-01), Meyer
patent: 0 079 576 (1983-05-01), None
S. Inque, et al. “Development of an FEC Combined Modem for DS-SSMA Communication System”, Globecom '90 IEEE Global Telecommunications Conference and Exhibition, vol. 2, Dec. 1990, p.746-750.
French Search Report dated Apr. 1, 1999, with annex on French Application No. 98/07721.

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