Radiation imagery chemistry: process – composition – or product th – Including control feature responsive to a test or measurement
Reexamination Certificate
2001-02-02
2003-06-10
Young, Christopher G. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Including control feature responsive to a test or measurement
C430S312000
Reexamination Certificate
active
06576385
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to an automated method of varying stepper exposure dose to compensate for across-wafer variations in photoresist thickness, and a system for accomplishing same
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
By way of background, an illustrative field effect transistor
10
, as shown in
FIG. 1A
, may be formed above a surface
15
of a semiconducting substrate or wafer
11
, such as doped-silicon. The substrate
11
may be doped with either N-type or P-type dopant materials. The transistor
10
may have a doped polycrystalline silicon (polysilicon) gate electrode
14
formed above a gate insulation layer
16
. The gate electrode
14
and the gate insulation layer
16
may be separated from doped source/drain regions
22
of the transistor
10
by a dielectric sidewall spacer
20
. The source/drain regions
22
for the transistor
10
may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate
11
. Shallow trench isolation regions
18
may be provided to isolate the transistor
10
electrically from neighboring semiconductor devices, such as other transistors (not shown).
The gate electrode
14
has a critical dimension
12
, i.e., the width of the gate electrode
14
, that approximately corresponds to the channel length
13
of the device when the transistor
10
is operational. Of course, the critical dimension
12
of the gate electrode
14
is but one example of a feature that must be formed very accurately in modern semiconductor manufacturing operations. Other examples include, but are not limited to, conductive lines, openings in insulating layers to allow subsequent formation of a conductive interconnection, i.e., a conductive line or contact, therein, etc.
In the process of forming integrated circuit devices, millions of transistors, such as the illustrative transistor
10
depicted in
FIG. 1A
, are formed above a semiconducting substrate. In general, semiconductor manufacturing operations involve, among other things, the formation of layers of various materials, e.g., polysilicon, insulating materials, etc., and the selective removal of portions of those layers by performing known photolithographic and etching techniques. These processes are continued until such time as the integrated circuit device is complete. Additionally, although not depicted in
FIG. 1A
, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate. These conductive interconnections allow electrical signals to propagate between the transistors formed above the substrate.
During the course of fabricating such integrated circuit devices, a variety of features, e.g., gate electrodes, conductive lines, openings in layers of insulating material, etc., are formed to very precisely controlled dimensions. Such dimensions are sometimes referred to as the critical dimension (CD) of the feature. It is very important in modern semiconductor processing that features be formed as accurately as possible, due to the reduced size of those features in such modern devices. For example, gate electrodes may now be patterned to a width
12
that is approximately 0.2 &mgr;m (2000 Å), and further reductions are planned in the future. As stated previously, the width
12
of the gate electrode
14
corresponds approximately to the channel length
13
of the transistor
10
when it is operational. Thus, even slight variations in the actual dimension of the feature as fabricated may adversely affect device performance. Thus, there is a great desire for a method that may be used to accurately, reliably and repeatedly form features to their desired critical dimension, i.e., to form the gate electrode
14
to its desired critical dimension
12
.
In modern semiconductor fabrication facilities, photolithography is a process typically employed in semiconductor manufacturing. Photolithography generally involves forming a patterned layer of photoresist above a layer of material that is desired to be patterned and using the patterned photoresist layer as a mask. In general, in photolithography operations, the pattern desired to be formed on the underlying layer of material is initially formed on a reticle. Thereafter, using an appropriate stepper tool and known photolithographic techniques, the image on the reticle is transferred to the layer of photoresist. Then, the layer of photoresist is developed so as to leave in place a patterned layer of photoresist substantially corresponding to the pattern on the reticle. This patterned layer of photoresist is then used as a mask in subsequent etching processes, wet or dry, performed on the underlying layer of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features or opening-type features, that are to be replicated in an underlying process layer. The features in the patterned layer of photoresist also have a critical dimension, sometimes referred to as a develop inspect critical dimension (DICD).
However, for a variety of reasons, the thickness of the layer of photoresist may not be uniform across the surface of the wafer, i.e., the thickness of the layer of photoresist may be greater than or less than the desired target thickness of the photoresist. Such variations may occur for a number of reasons. For example, there may be variations in the topology of one or more of the underlying films or process layers, the spinning process used to apply the photoresist to the wafer may be performed for too long or too short of a duration resulting in a layer of photoresist that is too thick or too thin. Additionally, there may be variations in the pre-bake process (sometimes referred to as soft-bake) prior to exposure in which various regions or sections of the wafer may be subjected to different temperatures, thereby, in a relative sense, locally driving off more solvents from the layer of photoresist thereby resulting in thickness variations. Of course, there may be other causes for across-wafer variations in photoresist thickness.
Moreover, such variations may be highly localized, or they may exhibit a recognizable pattern. For example, if one or more of the underlying process layers exhibits a large topographical discontinuity, e.g., a larger peak or valley, then the photoresist layer may be thinned or thickened, respectively, in the localized area of the discontinuity. Alternatively, it may be the case that the layer of photoresist is thinner in a central region of the wafer and thicker in outer regions of the wafer, or vice-versa. Thus, a variety of spatial variations in the photoresist thickness may be observed, including various recognizable patterns of thick
Bode Christopher A.
Hewett Joyce S. Oey
Pasadyn Alexander J.
Advanced Micro Devices , Inc.
Williams Morgan & Amerson P.C.
Young Christopher G.
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