Patent
1997-06-25
1999-02-23
Treat, William M.
G06F 930
Patent
active
058753168
ABSTRACT:
In a processor that executes complex instructions which are expanded into microinstructions prior to execution, non-complex instruction execution is optimized by providing a by-passable helper logic for expanding complex instructions into microinstructions. Control logic parses a bundle of instructions into sub-bundles of non-complex instructions and sub-bundles of microinstructions. The control logic detects when a complex instruction is present in a bundle of instructions and directs the complex instruction to the helper logic for expansion into two or more microinstructions. Each non-complex instruction bypasses the helper logic, thereby improving the execution performance of the non-complex instruction.
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Dakhil Dani Y.
Panwar Ramesh
Kubida William J.
Pinto James A.
Sun Microsystems Inc.
Treat William M.
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