Parallel and scalable instruction scanning unit

Details Parallel and scalable instruction scanning unit Parallel and scalable instruction scanning unit

1997-08-20

1999-02-23

Eng, David Y.

G06F 930

Patent

active

058753150

ABSTRACT:
An instruction scanning unit for a superscalar microprocessor is disclosed. The instruction scanning unit processes start and end byte information associated with a plurality of contiguous instruction bytes. The processing of start byte information and end byte information is performed independently and in parallel, and the instruction scanning unit produces a plurality of scan values which identify valid instructions within the plurality of contiguous instruction bytes. Additionally, the instruction scanning unit is scalable. Multiple instruction scanning units may be operated in parallel to process a larger plurality of contiguous instruction bytes. Furthermore, the instruction scanning unit detects certain error conditions. Error information may be used by external logic to determine the proper course of action in light of the detected error.

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