Abrading – Precision device or process - or with condition responsive... – Computer controlled
Reexamination Certificate
2001-02-02
2003-02-04
Eley, Timothy V. (Department: 3724)
Abrading
Precision device or process - or with condition responsive...
Computer controlled
C451S006000, C451S008000, C451S412000
Reexamination Certificate
active
06514122
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system for manufacturing a semiconductor and to a method of manufacturing a semiconductor, and more particularly, to management of a focus offset value employed during a lithography process.
2. Description of the Background Art
During a lithography step in a process of manufacturing a semiconductor device, an aligner has already been used as a system for manufacturing a semiconductor device, which the system utilizes the photolithography technique.
FIG. 6
is a cross-sectional view for describing a conventional system for manufacturing a semiconductor device.
The system for manufacturing a semiconductor device shown in
FIG. 6
substantially comprises an illumination system
1
, which is a light source for emanating exposure light; a reticle
2
having an exposure pattern drawn thereon; and a projection optical system
3
for radiating, in a scaled-down manner and onto a wafer
4
supported on a stage
5
, the light that has passed through the reticle
2
.
Reference numeral
41
designates a focus reference plane and shows the surface of a photoresist film (not shown) formed on the wafer
4
. The light projected by the projection optical system
3
is focused onto the focus reference plane
41
of the wafer
4
.
In a case where a focus is shifted to a position located above the focus reference place
41
, a positive focus offset value is set to the projection optical system
3
. Thus, the focus is aligned with the focus reference plane
41
of the water
4
.
In contrast, if a focus is shifted to a position located below than the focus reference plane
41
, a negative focus offset value is set to the projection optical system
3
, thus aligning the focus with the focus reference plane
41
.
As mentioned above, in the system for manufacturing a semiconductor device, a management of the focus offset value of the projection optical system
3
is important for accurate transfer. on to the wafer
4
, of the exposure pattern drawn on the reticle
2
.
Next will be described a conventional method of managing a focus offset value.
A manufacturing operation of the system for manufacturing a semiconductor device is ceased, and a bare silicon wafer
4
, which is coated with resist on one side, is placed on the stage
5
. A reticle
2
for use in manufacturing a product is replaced with a reticle
2
having drawn thereon a test pattern for managing a focus offset value.
The test patterns are patterned onto a plurality of positions on the wafer
4
through exposure while focus offset values are taken as parameters.
Specifically, the test pattern is patterned onto the wafer
4
through exposure while the first focus offset value (for example, +0.3 &mgr;m) is used. Next, the test pattern is again patterned in the vicinity of the area where the test pattern has been patterned by use of the first focus offset value, by means of exposure and through use of a second focus offset value (for example, +0.2 &mgr;m). Next, the test pattern is patterned onto the wafer
4
a plurality of times through use of the remaining focus offset values (for example, +0.1 &mgr;m, 0, −0.1 &mgr;m, −0.2 &mgr;m, and −0.3 &mgr;m).
Thus, a plurality of test patterns are formed on the wafer
4
while different focus offset values are used.
Next, the wafer
4
, on which the test patterns have been patterned by means of exposure and through use of the plural focus offset values, is developed. As a result, a plurality of test patterns corresponding to the plurality of focus offset values (−0.3 &mgr;m to +0.3 &mgr;m) are formed on the wafer
4
.
Next, the dimensions of the respective test patterns formed on the wafer
4
are measured through use of a critical dimension measurement SEM. If the dimensions of the test patterns satisfy standards, the maximum focus offset value and the minimum focus offset value are determined. A center value between the maximum and minimum focus offset values is managed as an optimum focus offset value.
In a case where test patterns are patterned through exposure for the purpose of leveling the stage
5
, a test pattern must be patterned onto a plurality of locations on the wafer
4
by means of exposure and through use of the previously-described focus offset values.
In order to manage a focus offset value, the conventional system for manufacturing a semiconductor device must periodically cease production. The management of a focus offset value involves repeated patterning of a pattern through use of different offset values a plurality of times and measurement of the thus-patterned patterns, thus consuming much time.
This results in an increase in down time of the system for manufacturing a semiconductor device, thus deteriorating an availability factor of the system for manufacturing a semiconductor device. Accordingly, there arises a problem of an increase in the cost of manufacturing a semiconductor device.
The management of a focus offset value is performed periodically. However, in the event that a variation arises in the focus offset value during a period between the periods of management, there is no way to find the variation until anomalous products are found.
In order to level the stage
5
, patterns must be patterned onto different locations on a wafer by means of multiple shots and through use of a single focus offset value. Similarly, patterns must be patterned onto a wafer by means of a plurality of shots through use of different focus offset values.
Thus, a long period of time is required for multiple shots and measuring the dimensions of patterns that have been developed. Therefore, the stage
5
can not be leveled easily.
SUMMARY OF THE INVENTION
The present invention has been conceived to solve the previously-mentioned problems and a general object of the present invention is to provide a novel and useful system for manufacturing a semiconductor device, and is to provide a novel and useful method of manufacturing a semiconductor device, and is to provide a semiconductor device manufactured by the method.
A more specific object of the present invention is to manage a focus offset value without suspending manufacture of a semiconductor device in a system for manufacturing a semiconductor device.
Another more specific object of the present invention is to monitor a focus offset value even during a period of time between periods of management of a focus offset value
Another more specific object of the present invention is to level a stage for supporting a product wafer easily.
The above objects of the present invention are attained by a following system for manufacturing a semiconductor device, and by a following method of manufacturing a semiconductor device.
According to one aspect of the present invention, the system for manufacturing a semiconductor device comprises a stage for supporting a product wafer; an illumination system for emanating exposure light; a reticle which has drawn thereon a test pattern for managing a focus offset value and a product pattern, and through which the light originating from the illumination system passes; a projection optical system for projecting, onto the product wafer and at a desired focus offset value, the light that has passed through the test pattern and the product pattern drawn on the reticle; and an adjustment section for adjusting the focus offset value of the projection optical system on the basis of a measurement result of dimension of the test pattern, which pattern is patterned onto the product wafer through exposure.
In the system for manufacturing a semiconductor device, since a management of a focus offset value can be carried out in conjunction with manufacture of semiconductor products, the availability factor of the system for manufacturing a semiconductor device can be improved.
According to another aspect of the present invention, in a manufacturing method of a semiconductor device, a product pattern is patterned onto a product wafer through exposure as well as patterning a test pattern for man
Matsushita Takuya
Miyagi Tadashi
Saito Takayuki
Eley Timothy V.
Mitsubishi Denki & Kabushiki Kaisha
LandOfFree
System for manufacturing semiconductor device utilizing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System for manufacturing semiconductor device utilizing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System for manufacturing semiconductor device utilizing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3144138