Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-10-29
2003-12-30
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S720000, C438S745000, C438S750000, C438S283000, C438S299000, C438S300000, C216S067000
Reexamination Certificate
active
06670277
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device including a wiring structure or a gate electrode structure of a MOSFET (metal oxide semiconductor field effect transistor) formed on a semiconductor substrate.
2. Description of the Background Art
A conventional method of manufacturing a MOSFET, for example, will be set forth with reference to
FIGS. 12
to
17
. First, a gate insulating film
40
and a non-single crystalline silicon film
50
are formed on a semiconductor substrate
10
such as a silicon substrate, in the surface of which a well
30
and an element isolation film
20
are formed (FIG.
12
).
Then, a photoresist is formed on the non-single crystalline silicon film
50
and is patterned by a photolithographic technique for formation of a gate electrode. The non-single crystalline silicon film
50
is etched using the photoresist as a mask and a gate electrode is formed by the removal of the photoresist (FIG.
13
).
Subsequent ion implantation
100
(
FIG. 14
) produces source/drain extension layers
60
in the well
30
. If the ionic species to be implanted has to be changed depending on the type, p-type or n-type, of the well
30
, one side of the well
30
should be covered as necessary with the photoresist.
Then, an insulating film to cover the gate insulating film
40
and the non-single crystalline silicon film
50
is formed and etched to form gate sidewall protection films
70
(FIG.
15
). At this time, as shown in
FIG. 15
, portions of the gate insulating film
40
, which are not covered with the non-single crystalline silicon film
50
and the gate sidewall protection films
70
, can also be removed.
Following ion implantation
110
(
FIG. 16
) produces source/drain regions
80
in the well
30
. Here again, if the ionic species to be implanted has to be changed depending on the type, p-type or n-type, of the well
30
, one side of the well
30
should be covered as necessary with the photoresist. Further, thermal processing may be performed for recovering damage from the ion implantation.
Then, a metal film (Co, etc.) to cover the gate electrode and the substrate is formed by sputtering, and through thermal processing, silicide layers
90
of CoSi
2
, etc., are formed in the surface of the gate electrode of the non-single crystalline silicon film
50
and in the surface of the source/drain regions
80
(FIG.
17
). At this time, the unreacted metal film is removed and residual compounds are changed into the silicide layers
90
through appropriate thermal processing.
In the aforementioned MOSFET manufacturing method, the patterning of the non-single crystalline silicon film
50
during the transition from the step of
FIG. 12
to that of
FIG. 13
may be done with the photoresist, or alternatively, it may be done with a material of higher physical strength than the photoresist, such as a silicon oxide film, as an etching mask (such an etching mask is hereinafter referred to as a “hard mask”).
In such a case, a hard mask
55
is formed after the step of
FIG. 12
(
FIG. 18
) and a photoresist is formed on the hard mask
55
and is patterned by the photolithographic technique for formation of a gate electrode.
The hard mask
55
is then etched using the photoresist as a mask and the photoresist is removed (FIG.
19
). During the etching of the hard mask
55
, the non-single crystalline silicon film
50
also is somewhat etched, causing a difference in level
50
a
as shown in FIG.
19
. This, however, can be prevented by setting a high etch selectivity between the non-single crystalline silicon film
50
and the hard mask
55
.
The non-single crystalline silicon film
50
is etched using the hard mask
55
as a mask, whereby a gate electrode is formed (FIG.
20
).
The use of the hard mask
55
as a mask brings the following advantages. If a material with great controllability over etching, such as a silicon oxide film, is used as a hard mask, finer patterning can be achieved with additional isotropic etching after the step of
FIG. 19
(FIG.
21
). If this hard mask is used as a mask for the patterning of the non-single crystalline silicon film
50
, a gate electrode of smaller dimensions can be formed (FIG.
22
).
Taking, for example, a KrF excimer laser which is commonly used as a light source in the current photolithographic technique. Since the laser has a wavelength of 0.248 &mgr;m, exposure only is not enough to achieve a gate length on the order of 0.1 &mgr;m. However, the use of the aforementioned material with great controllability over etching as a hard mask allows patterning for formation of a gate electrode of smaller dimensions as shown in FIG.
21
.
While the above description refers to the method of manufacturing a gate electrode of a MOSFET, the same process as shown in
FIGS. 12 and 13
is also applicable to the formation of a wiring structure on the substrate.
Now, it is effective for MOSFETs to reduce their gate lengths for higher performance and higher integration density. Also in the formation of a wiring structure, a reduced width of wiring is required for higher integration density.
In forming elements in a wafer, however, it is difficult to provide uniform exposure in the photolithographic process since the crowdedness of the pattern is generally different in each location. More specifically, such a difference in the pattern crowdedness varies the reflection of a light beam during exposure and thereby makes it difficult to transfer the pattern as designed on the photoresist. It is thus not easy to uniformly reduce the gate lengths in the wafer surface.
To reduce variations occurring during process due to variations in the pattern crowdedness, anti-reflection coatings (ARC) have been introduced. The anti-reflection coatings are films for preventing a transmitted light which passes through a resist during exposure in the photolithographic process from reflecting and adversely effecting design dimensions such as the gate length. Specifically, a silicon oxy-nitride film, for example, serves as a material for the anti-reflection coatings.
The anti-reflection coatings come in two types: those for filling irregularities of the pattern crowdedness and those for preventing the occurrence of multiple reflections which is a phenomenon that repeated reflections of the transmitted light occur between the substrate and the resist. Herein, the latter anti-reflection coatings shall be noted.
When the anti-reflection coating is introduced into the aforementioned semiconductor device manufacturing method using a hard mask, the following problems arise. A silicon oxy-nitride film, for example, is a material which is difficult to increase etch selectivity to silicon. Using such a silicon oxy-nitride film for the anti-reflection coating makes it difficult to etch only the anti-reflection coating without etching the substrate and the gate electrode in a process where the silicon substrate and the polysilicon gate electrode are exposed.
This will be described with reference to
FIGS. 23
to
29
. After the step of
FIG. 18
, an anti-reflection coating
56
is formed over the whole surface of the hard mask
55
(FIG.
23
). At this time, the anti-reflection coating
56
is not directly formed on the non-single crystalline silicon film
50
in order to prevent the non-single crystalline silicon film
50
from being etched upon completion of the etching of the anti-reflection film
56
and thereby to prevent the occurrence of variations in the height of the gate electrode, when a material which is difficult to increase etch selectivity to silicon, such as a silicon oxy-nitride film, is used for the anti-reflection coating
56
.
Following this, a photoresist is formed on the anti-reflection coating
56
and is patterned by the photolithographic technique for formation of a gate electrode. The anti-reflection coating
56
and the hard mask
55
are then etched using the photoresist as a mask and the photoresist is removed (FIG.
24
).
During the etching of the hard mask
Okumura Yoshinori
Sayama Hirokazu
Norton Nadine G.
Renesas Technology Corp.
Vinh Lan
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