Method and apparatus for modulating and demodulating digital...

Coded data generation or conversion – Digital code to digital code converters – To or from run length limited codes

Reexamination Certificate

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C341S068000

Reexamination Certificate

active

06670896

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method and an apparatus for modulating or encoding digital data. In addition, this invention relates to a method and an apparatus for demodulating or decoding digital data. Furthermore, this invention relates to a recording medium loaded with modulation-resultant digital data.
2. Description of the Related Art
Some digital data recording or transmission includes a step of “channel coding” which is also called “modulation”. The channel coding is as follows. Each block (for example, each byte) of digital data to be recorded or transmitted is modulated into a code word. The resultant code words are serially connected so that the digital data are converted into a code-word sequence in the form of a bit stream. It is desirable that the code-word sequence to be recorded matches the characteristics of a related recording medium or a related transmission channel.
In the case of recording on an optical disc, it is good for recorded digital data to satisfy the following constraints: 1) a minimum zero-run-length constraint (that is, a minimum pit or land length constraint) due to optical transmission characteristics in recording and reading and to physical restrictions involved in pit formation, 2) a maximum zero-run-length constraint (that is, a maximum pit or land length constraint) for the facilitation of a clock-signal recovery, and 3) a constraint on low-frequency signal components for the sake of servo control.
Known modulation systems for digital signals to be recorded include an EFM (eight-to-fifteen modulation) system for compact discs (CDs) and an EFMPlus (eight-to-sixteen modulation) system for digital versatile discs (DVDs). The EFM and EFMPlus systems provide modulation-resultant digital signals which satisfy constraints such that a minimum zero-run-length and a maximum zero-run-length are equal to 3T and 11T respectively, where T denotes a channel bit period.
Specifically, the EFM system encodes every 8-bit block of digital data into a 14-channel-bit code word, and connects the resultant code words while inserting sets of 3 margin bits therebetween. Thus, the EFM system modulates the digital data into a margin-bit-added code-word sequence by conversion from 8 bits to 17 bits. The resultant code-word sequence is in the form of a bit stream. In addition, the resultant code-word sequence is designed to satisfy “RLL(2, 10)” which means run length limiting rules such that 2 to 10 successive channel bits of “0” should be between channel bits of “1”. Even at every connection between code words via margin bits, RLL(2, 10) is observed. Since RLL(2, 10) is satisfied, direct-current and low-frequency components of the resultant code-word sequence are suppressed.
The EFMPlus system encodes every 8-bit block of digital data into a 16-bit code word, and serially connects the resultant code words without inserting margin bits therebetween. Thus, the EFMPlus system converts the digital data into a code-word sequence without margin bits by conversion from 8 bits to 16 bits. The resultant code-word sequence is in the form of a bit stream. In addition, the resultant code-word sequence is designed to satisfy RLL(2, 10).
U.S. Pat. No. 6,297,753 B1 corresponding to Japanese patent application publication number P2000-286709A discloses a modulation system for encoding every “p”-bit block of digital data into a “q”-bit code word, serially connecting the resultant code words, and thereby converting the digital data into a code-word sequence in the form of a bit stream which observes run length limiting rules such that a minimum zero-run-length and a maximum zero-run-length are equal to 3T and 11T respectively. The modulation system in U.S. Pat. No. 6,297,753 B1 includes a plurality of encoding tables for converting “p”-bit input data words into “q”-bit output code words. Each of the encoding tables lists output code words and state-information pieces assigned to input data words. The state-information pieces are designed to select one among the encoding tables which will be accessed for the conversion of a next input data word. Furthermore, the group of encoding tables is designed so that the NRZI modulation results of output code words in specified encoding tables which are assigned to each predetermined input data word are opposite in parity or polarity (“odd-even” in the number of bits of “1”). This design of the encoding tables is utilized in performing DSV (digital sum value or digital sum variation) control of the output-code-word sequence.
In an example of the modulation system of U.S. Pat. No. 6,297,753 B1, the numbers “p” and “q” are equal to 8 and 15 respectively. Accordingly, the modulation system implements conversion from 8 bits to 15 bits for modulating digital data into a code-word sequence.
The documents SPIE, Vol. 4090, pages 275-282, which are written by W. Coene and E. Chuang, disclose “EFMCC: A New Combi-Code for High Density Optical Recording”. According to the documents SPIE, EFMCC is a run-length-limited (RLL) channel code with EFM-like RLL constraints, RLL(2, 10), which is constructed by combining two codes, a main code and a substitution code. Both codes operate on a byte-by-byte basis. The substitution code has a special structure, i.e., for each byte, there are two possible channel words, which have opposite parity and the same next-state in the finite-state machine of the EFMCC code. The benefits are: guaranteed DC-control, 4% higher efficiency than EFMPlus, and simple byte-oriented look-ahead DC-control encoding.
Specifically, the Comb-Code implies a combination of two channel codes C
1
and C
2
, which both operate on a byte-by-byte basis. Code C
1
is called the main code, and maps a byte into a 15-bit channel word: its goal is to realize a high coding rate. Code C
2
is called the substitution code, and maps a byte into one out of two possible 17-bit channel words: its goal is to realize a guaranteed DC-control (direct-current-control), at the cost of a lower rate. For each of the coding states of the underlying finite-state machine (FSM), both 17-bit channel words of the substitution code C
2
have to satisfy two conditions: (i) both channel words have opposite parity and (ii) both channel words have the same next-state in the FSM. Every byte encoded with the substitution code C
2
represents a DC-control point in the channel bit stream since the parity selection at C
2
determines the polarity, and thus the contribution to the RDS (running digital sum) value, of the channel bit stream for the subsequent bytes all encoded with the main code C
1
, up to the next byte encoded with C
2
. Apart from the polarity, the channel bit stream for the bytes encoded with the main code C
1
does not depend on the parity selection at the substitution code C
2
, i.e., the corresponding (d, k) sequences are identical.
The EFMPlus system uses conversion from 8 bits to 16 bits while the EFM system implements conversion from 8 bits to 17 bits. Therefore, the EFMPlus system is better in coding efficiency than the EFM system by about 6%.
The modulation system in U.S. Pat. No. 6,297,753 B1 uses conversion from 8 bits to 15 bits while the EFMPlus system implements conversion from 8 bits to 16 bits. Therefore, the former system is better in coding efficiency than the latter system by about 6.67%. In the modulation system of U.S. Pat. No. 6,297,753 B1, since the DSV control is of a probability-based type, the DSV has a chance of diverging when digital data assume a specified pattern.
In the EFMCC system or the Comb-Code system, two C
2
maps (encoding tables) for generating two possible 17-bit channel words in response to an input byte are required to implement DSV control. Thus, the size of encoding tables is relatively large. Since the encoding of input bytes with a C
1
map hardly contributes to the DSV control, the frequency of the execution of the DSV control is limited to a relatively low value.
SUMMARY OF THE INVENTION
It is a first object of this invention to provide a method of modulating digital data

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