Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-04-11
2003-10-21
Zarabian, Amir (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S703000, C430S312000
Reexamination Certificate
active
06635581
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a method for forming a thin-film transistor (TFT). In particular, the present invention relates to a method for forming a pattern with different depths by an etching process.
2. Description of the Related Art
The TFT is an active element commonly used in a liquid crystal display (LCD). During the addressing period for inputting the image data, the semiconductor layer of the TFT has a low resist value (the “on” state), and the image data is written into a capacitor and the orientation of the liquid crystal molecules are changed. In the sustaining period, the semiconductor layer of the TFT has a high resist value (the “off” state), and the image data is maintained.
The conventional TFT used in the flat display panel is shown in
FIG. 1
, and its manufacturing process is described below. The substrate
10
has a TFT region, and a first metal layer is formed in the TFT region. The first metal layer is patterned to form a gate line
12
along a first direction by a first lithography and etching process. An insulating layer
14
, a semiconductor layer
16
, an n-doped silicon layer
18
and a second metal layer
20
are sequentially deposited on the gate line
12
. The semiconductor layer
16
can be an amorphous silicon layer. A second lithography and etching process is used to pattern the amorphous silicon layer
16
, the n-doped silicon layer
18
and the second metal layer
20
to expose the insulating layer
14
. The second metal layer
20
is also patterned to form a signal line along a second direction, and the second direction is vertical to the first direction. The third lithography and etching processes are conducted to define a channel
19
in the second metal layer
20
and the n-doped silicon layer
18
so as to expose the amorphous silicon layer
16
in the channel
19
. A source electrode and a drain electrode are formed and separated by the channel
19
.
The conventional manufacturing method needs several lithography and etching processes to form the TFT, and is a time-consuming and costly procedure. An alternate method is proposed to pattern the second metal layer and form the channel in one lithography and etching process by using a photoresist layer having different depths. In other words, the second and third lithography and etching processes are combined into one lithography and etching process, thus the manufacturing time and cost can be reduced. The patterned photoresist layer with different depths can be formed by several exposure methods. For example, “slit mask” exposure method is used to pattern the photoresist layer to form different depths, as disclosed in “FPT Intelligence”, May 1995, p.31. In addition, a “Halftone mask” exposure method is also used to pattern the photoresist layer to form different depths, as disclosed in Japanese LCD technical literature, volume 4, p.61. Further, a double exposure method can be used to pattern the photoresist layer.
While using the above-mentioned methods to form the photoresist layer with different depths, the material of the photoresist layer will be an important factor. It is a serious problem to choose one photoresist layer appropriate for the “slit mask”, “halftone mask”, or double exposure method. In other words, forming one photoresist layer with different depths by one exposure method is difficult. By only one exposure process, the accuracy of the patterns on the photoresist layer is poor, and the condition of the exposure process is also hard to maintain. Therefore, the yield of the TFT manufacturing process will be reduced.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a method of forming a thin film transistor (TFT) in which the signal line and the channel can be formed in one process so as to reduce the cost and time.
Another object of the present invention is to provide a method of forming a TFT using multiple photoresist layers with different absorptivities to form the signal line and the channel in one process.
Still another object of the present invention is to provide a method of forming a TFT using multiple photoresist layers with different photosensitivities to form the signal line and the channel in one process.
To achieve the above-mentioned object, a method for forming a thin film transistor (TFT) is provided. In this method, a gate electrode, an insulating layer, a semiconductor layer, a doped silicon layer and a metal layer are formed on a substrate. A first photoresist layer is formed on the metal layer. A second photoresist layer is formed on the first photoresist layer. An exposure process and a development process are performed to form a first pattern on the first photoresist layer and a second pattern on the second photoresist layer at the same time. An etching process is performed to transfer the first pattern on the semiconductor layer, the doped silicon layer and the metal layer, and also transfer the second pattern on the doped silicon layer and the metal layer. The first photoresist layer and the second photoresist layer are removed.
The absorptivity or photosensitivity of the first photoresist layer is lower than that of the second photoresist layer. Moreover, an adhesion layer can be alternatively formed between the first photoresist layer and the second photoresist layer. The method of patterning the first photoresist layer and the second photoresist layer is selected from a group of multiple exposure, halftone mask exposure, and slip mask exposure.
The step of performing the etching process is performed as follows. The semiconductor layer, the doped silicon layer and the metal layer are etched by using the first photoresist layer and the second photoresist layer as a mask, so as to transfer the first pattern on the above layers. The second pattern is transferred on the first photoresist layer by using the second photoresist layer as a mask. The doped silicon layer and the metal layer are then etched by using the first photoresist layer with the second pattern as a mask, so as to transfer the second pattern on the doped silicon layer and the metal layer.
Further, a method for forming an element is provided. A first photoresist layer is formed on a layer to be etched. A second photoresist layer is formed on the first photoresist layer. An exposure process and a development process are performed to form a first pattern in the first photoresist layer and a second pattern in the second photoresist layer at the same time. After etching process is performed to transfer the first pattern and the second pattern into the layer, the first photoresist layer and the second photoresist layer are removed.
REFERENCES:
patent: 5091339 (1992-02-01), Carey
patent: 5286607 (1994-02-01), Brown
patent: 5494839 (1996-02-01), Hong et al.
patent: 5700626 (1997-12-01), Lee et al.
patent: 5741624 (1998-04-01), Jeng et al.
patent: 6221542 (2001-04-01), Reinberg
patent: 6350674 (2002-02-01), Okamura
“Technical Report”, FPT Intelligence, pp. 31-33 (May, 1995).
Japanese LCD Technical Literature, vol. 4, pp.61.
AU Optronics Corp.
Brophy Jamie L.
Ladas & Parry
Zarabian Amir
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