Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Electrical signal parameter measurement system
Reexamination Certificate
2000-12-06
2003-10-28
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Electrical signal parameter measurement system
C702S032000, C702S057000, C702S106000, C714S751000, C714S758000, C375S226000, C375S227000, C370S516000, C370S503000, C340S315000, C340S146200, C324S613000, C324S620000
Reexamination Certificate
active
06640193
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of electronic circuits and more specifically to a method and system for measuring jitter.
BACKGROUND OF THE INVENTION
The growing use of data converters has created a demand for more accurate and more precise methods for measuring jitter. Sampling time noise, or jitter, is a component of signal-to-noise ratio (SNR), which is an important parameter in assessing the performance of a data converter. Jitter causes deviations in the sampling time, which in turn causes deviations in the value of the signal sample. Jitter becomes a major factor in the SNR at relatively high input frequencies, for example, the frequencies at which communications analog-to-digital converters (ADCs) operate, because even a small deviation in the sampling time may result in a large deviation in the value of the signal sample. As the demand for intermediate frequency sampling in communication systems increases, ADC manufacturers are faced with the task of measuring the SNR at very high input frequencies. The SNR at high input frequencies may be measured using a test system with very low jitter. Even state-of-the-art test systems, however, cannot meet the low jitter requirement. Alternatively, the SNR may be measured using test systems with medium jitter by measuring the jitter of the system and then calibrating out the jitter. Known methods and systems of measuring jitter, however, have not been completely satisfactory in terms of accuracy, precision, and speed.
Calculation of the maximum jitter tolerance for a data converter begins with computing the SNR. Theoretically, the best possible SNR of an N-bit converter, assuming that the input is uniformly distributed between two adjacent data converter codes, is given by Equation (1):
SNR
max(
dBs
)=6.02
N~
6
N
(1)
Practically, the measured SNR of a data converter may be worse than the above prediction due to various factors, including jitter. Overall jitter may be due to internal factors inside of the data converter such as the aperture jitter of a sample and hold circuit or to external factors such as the jitter of a dock source or the phase noise of an input wave generator. If the amplitude noise due to overall jitter is integrated and the input is a sine wave, Equation (2) describes how overall jitter limits the best SNE of a data converter:
SNR
max(
dBs
)=−20 log(2
nf
&egr;) (2)
where f is the input frequency, and &egr; is the root mean square (mis) value of the overall jitter in the system. Assuming that the jitter induced noise level should be Less than the quantization noise of an ideal converter, Equations (1) and (2) may be equated to yield Equation (3) describing the maximum jitter tolerance a of a data converter:
ϵ
<
1
f
*
10
0.3
N
*
2
π
(
3
)
According to Equation (3), less than 1 ps rms jitter is tolerated in a 14-bit communication ADC sampling a 70 MHz if signal. This requirement is very stringent considering the fad that the typical jitter found in CMOS digital logic circuits is around 20-30 ps rms. Other maximum jitter tolerance levels are shown in TABLE 1.
TABLE 1
Maximum Jitter Tolerance for ADCs (ps rms × 2&pgr;)
Bits
8
10
12
14
16
Input
Frequency:
10 KHz
398107
100000
10000
6309
1585
100 KHz
39810
10000
1000
631
158
1 MHz
3981
1000
100
63
15.8
10 MHz
398
100
10
6.3
1.58
100 MHz
40
10
1
0.63
0.16
The stringent low jitter requirement makes the measurement of the SNR of data converters extremely difficult. According to a known approach for measuring the SNR, the SNR is directly measured. This approach requires that the jitter of the system used to measure the SNR of the data converter be much lower than the maximum jitter tolerance level. Low jitter sine wave generators and clock sources, however, are very expensive and often fail to meet the performance requirements needed to measure the SNR of communication ADCs. Moreover, it is difficult to integrate low jitter sine wave generators and clock sources into production testers. In another approach for measuring the SNR, instead of using an ideal clock source or sine wave generator to minimize system jitter, the noise due to system jitter is measured and calibrated out from the overall noise. Such calibration techniques, however, remove the requirement for low jitter hardware at the expense of the need for accurate and precise jitter measurements. For such calibration to work, the accuracy of the jitter measurement has to be much better than the jitter in the test system.
Known methods of measuring jitter include the sampling scope methods, comparator methods, and phase noise methods. According to the sampling scope methods, a clock waveform is digitized at a high speed and the time between the two signals edges is measured. Jitter is computed from the standard deviation of the measurements. A disadvantage of these methods is that the scope timebase must be jitter-free. Moreover, the accuracy of these methods is limited to approximately 10 ps rms, partly due to the insufficient 8-bit resolution of the ADCs used in scopes. The comparator methods use a comparator to trigger at the zero crossings of the clock and start a coarse and a fine counter. The fine counter works by digitizing the discharge voltage of a capacitor. The coarse counter takes the average of multiple measurements of the time between the zero crossings. These methods, however, are slow. Moreover, the accuracy of these methods is limited to approximately 10 ps rms. The phase noise methods measure the phase noise and mathematically relate the phase noise to clock jitter. These methods, however, require a very low phase noise signal generator and a high quality mixer to mix down the fundamental components of the clock frequency to the base band. Moreover, these methods are frequency-based and are very slow.
While these approaches have provided improvements over prior approaches, the challenges in the field of electronic circuits have continued to increase with demands for more and better jitter measurement techniques having greater accuracy and precision. Therefore, a need has arisen for a new method and system for measuring jitter.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method and system for measuring jitter are provided that substantially eliminate or reduce the disadvantages and problems associated with previously developed systems and methods.
According to one embodiment of the present invention, a system for measuring overall jitter is disclosed that comprises a data converter and a signal generator. The signal generator is coupled to the data converter and outputs a signal to the data converter. The data converter measures the signal to generate a first measurement set representing overall jitter and system noise, and to generate a second measurement set representing system noise. The overall jitter is computed using the first measurement set and the second measurement set. More specifically, the overall jitter is computed using the variance of the first measurement set and the variance of the second measurement set.
According to one embodiment of the present invention, a method for measuring overall jitter is disclosed. First, a signal is input into a data converter. Second, a first measurement set representing overall jitter and system noise is generated by measuring the signal. Third, a second measurement set representing system noise is generated by measuring the signal. Finally, the overall jitter is computed using the first measurement set and the second measurement set. More specifically, the overall jitter is computed using the variance of the first measurement set and the variance of the second measurement set.
According to one embodiment of the present invention, a system for measuring internal jitter is disclosed that comprises a signal generator that generates a signal. A splitter coupled to the signal generator splits the signal into an input signal and a clock signal. A data converter coupled to the splitter measur
Brady III W. James
Desta Elias
Hoff Marc S.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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