Digital video signal processing apparatus and method...

Motion video signal processing for recording or reproducing – Local trick play processing – With randomly accessible medium

Reexamination Certificate

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Details

C386S349000

Reexamination Certificate

active

06526224

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital video signal processing apparatus for compression-encoding a digital video signal as blocks, a method thereof, and a digital video signal reproducing apparatus thereof.
2. Description of the Related Art
A digital video tape recorder that records/reproduces a digital video signal has been practically used (hereinafter the digital video tape recorder is referred to as DVTR). In the DVTR, digital video data is compressed, encoded with error correction code, and then recorded to a record medium such as a magnetic tape.
FIG. 1
is a block diagram showing an example of the structure of the DVTR. For example, digital video data as record data is supplied to a BRR (Bit Rate Reduction) encoder
101
through an interface
100
. The BRR encoder
101
compresses and encodes the record data corresponding to for example DCT (Discrete Cosine Transform) method. The encoded record data is supplied to an error correction code encoder
102
that encodes the record data with for example product code.
The error correction code encoder
102
is connected to a RAM (not shown). Data supplied to the error correction code encoder
102
is written to the RAM. The error correction code encoder
102
generates outer code parity for the record data written to the RAM in the column direction with Reed-Solomon code and likewise generates inner code parity thereof in the line direction. Thus, the error correction code encoder
120
encodes the record data with product code. The data size of product code as inner code and outer code is referred to as error correction block.
The error correction encoder
102
reads the encoded record data from the RAM in the row direction and supplies the resultant data to a record driving portion
103
that includes a recording amplifier. Thereafter, a magnetic head
104
records the data received from the record driving portion
104
to a magnetic tape
105
.
At this point, the data is recorded corresponding to a helical scan method of which the magnetic head
104
is disposed on a rotating drum and the magnetic head
104
forms slanted tracks on the magnetic tape
105
. In addition, the data is recorded corresponding to an azimuth recording method of which azimuth angles of adjacent two tracks are different.
FIGS. 2A
,
2
B,
3
A, and
3
B show examples of structures of the above-described error correction blocks. In these examples, data of one frame is composed of 12 tracks formed on a magnetic tape
105
. In addition, a segment is composed of a pair of adjacent two tracks with different azimuth angles. Thus, one frame is composed of 12 tracks (=six segments). These segments are assigned segment numbers
0
to
5
.
In the example of video data shown in
FIGS. 2A and 2B
, one track of 12 frames forms one error correction block shown in FIG.
2
B. For example, data of each column is encoded in the direction of arrow b with (
250
,
226
) Reed-Solomon code. Thus, outer code parity of 24 bytes is formed. In addition, the resultant video data and the outer code parity are encoded in the direction of arrow a with (
229
,
217
) Reed-Solomon code. Thus, inner code parity of 12 bytes is formed. Sync data of two bytes and ID of two bytes are placed at the beginning of each data row.
FIGS. 3A and 3B
show an example of the structure of an error correction block of audio data. As shown in
FIG. 3A
, in audio data, one error correction block is composed of six tracks in 12 tracks of one frame. For example, audio data composed of a data array of 217 bytes×12 bytes is encoded in the direction of arrow b with (
24
,
12
) Reed-Solomon code. Thus, outer code parity of 12 bytes is formed. In addition, the resultant data and the outer code parity are encoded in the direction of arrow a with for example (
229
,
217
) Reed-Solomon code. Thus, inner code parity of 12 bytes is generated. Moreover, sync data and ID are placed at the beginning of each data row.
FIG. 4
is a schematic diagram showing an example of the structure of one sync block of an error correction block of video data. Referring to
FIG. 4
, the first two bytes are sync data. The sync data is followed by ID of two bytes. The ID represents a unique number of the current sync block in one track (segment number) or an unique sync block number. The ID is followed by video data of 217 bytes (or outer code parity) and inner code parity. Record data on the magnetic tape is composed of a sequence of sync blocks.
Data recorded on the magnetic tape
105
is read as reproduction data by a magnetic head
106
. The reproduction data is supplied to an inner code decoder
108
through an equalizer
107
. The inner code decoder
108
decodes the reproduction data with inner code using a RAM
109
connected thereto. In other words, the inner code decoder
108
corrects an error of each row corresponding to inner code parity placed thereto. When the number of errors exceeds the error correction capability of the code and errors remain, the inner code decoder
109
sets an error flag to all symbols of the row. The inner code decoder
108
writes error corrected reproduction data to the RAM
109
.
The inner code decoder
108
reads the error corrected reproduction data in the column direction of the product code from the RAM
109
and arranges the data. sequence in the direction of the outer code. The inner code decoder
108
supplies the resultant reproduction data to an outer code decoder
110
. The outer code decoder
110
corrects an error of data with the outer code. In other words, the outer code decoder
110
corrects an error of each column of the data corresponding to outer code parity placed thereto. The outer code decoder
110
uses outer code and the error flag placed to each symbol by the inner code decoder
108
. The outer code decoder
110
writes the error corrected reproduction data to a RAM
111
connected thereto.
As the error corrected result, the outer code decoder
110
sets an error flag to each symbol. The error flag represents that an error remains in the case that the number of errors exceeds the error correction capability of the code and the outer code decoder
110
cannot correct the errors of the data.
The outer code decoder
110
reads the resultant reproduction data that has been corrected with outer code in the row direction from the RAM
111
. Thus, the read direction that has been changed in the RAM
109
is restored to the original read direction.
The resultant reproduction data that has been corrected with inner code and outer code is supplied to a BRR decoder
112
. The BRR decoder
112
decodes the reproduction data that has been compressed and encoded. Output data of the BRR decoder
112
is supplied as digital video data to the outside of the DTVR through an interface
113
.
Data with the error flag that represents an error thereof has not been corrected by the outer code decoder
110
is concealed corresponding to for example interpolating method.
As described above, in the DVTR, to effectively record/reproduce data to/from a record medium, when a video signal is recorded, it is compressed and encoded corresponding to for example DCT method. In this method, video data is divided into DCT blocks each of which is composed of 8×8 pixels. DCT coefficients are obtained for each DCT block. In addition, corresponding to the obtained DCT coefficients, data is compressed and encoded. In such a compressing and encoding method, the size of data that has been compressed varies corresponding to DCT coefficients of each DCT block. In other words, the required data amount largely varies corresponding to the complexity of an image that data of the DCT block represents as shown in
FIGS. 5A and 5B
.
In
FIG. 5A
, each of areas A to E surrounded by dotted lines corresponds to DCT blocks for one sync block. In FIGS.
5
B and similar drawings, the left side represents a low frequency component side (including DC component) of DCT coefficients, whereas the right side represents a high frequency component side. I

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