Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
2001-04-19
2003-10-07
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S059000, C257S765000, C349S139000, C349S148000, C349S152000
Reexamination Certificate
active
06630688
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to contact structures of wirings and methods for manufacturing the same, and thin film transistor array panels including the same and methods for manufacturing the same.
(b) Description of the Related Art
Generally, wiring of semiconductor devices is to transmit signals without delay.
In order to prevent delay or distortion of signals, materials having a low resistivity such as aluminum or aluminum alloys are generally used. However, the physical and the chemical properties of the aluminum or aluminum alloy is not good. In other words, the aluminum or aluminum alloy is easily oxidized and broken, when connecting other conductive material in a contact portions. Accordingly, the characteristics of semiconductor devices are deteriorated. Especially, it causes problems when ITO (indium tin oxide) as a transparent electrode such as in a liquid crystal display is used to reinforce pad portions of aluminum. However, because of the poor contact properties between aluminum or aluminum alloy and indium tin oxide (ITO), the aluminum or aluminum alloy must be removed to prevent the corrosion of aluminum and aluminum alloy and a different material is then inserted therebetween. Accordingly, the manufacturing method is complicated and production costs are increased.
In general, a thin film transistor array panel is manufactured by a photolithography process. Since the photolithography process is expensive, the number of the photolithography steps needs to be minimized.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide contact structures having good contact properties of wiring made of a material of low resistivity and methods for manufacturing the same.
It is another object of the present invention to provide a thin film transistor array panels having contact structures of good contact properties and methods for manufacturing the same.
It is another object of the present invention to simplify manufacturing methods of thin film transistor array panels for liquid crystal displays.
These and other objects are provided, according to the present invention, by forming a wire made of a metal of aluminum-based material and a conductive layer, which is connected to the wire, made of indium zinc oxide.
In a manufacturing method of a contact structure of a wire, a wire made of a metal layer including aluminum-based material is formed, and an insulating layer covering the wire is deposited. Then, the insulating layer is patterned to form a contact hole exposing the wire, and a conductive layer, which is electrically connected to the wire and made of indium zinc oxide, is formed.
It is desirable that the insulating layer is made of nitride silicon, and the insulating layer is deposited in the range of 280-400° C. and during 5-40 minute, to include anneal process.
The contact structure of the wire and the method for manufacturing the same may be adapted to a manufacturing method of a thin film transistor array panel.
A gate wire including a gate pad and made of a metal layer of aluminum-based material is formed, and a gate insulating layer covering the gate wire is formed. A semiconductor layer and a data wire are sequentially formed, then the gate insulating layer is patterned to form a contact hole exposing the gate pad. Next, a conductive layer made of indium zinc oxide (IZO) and connected to the gate pad is formed.
It is desirable that the gate insulating layer of nitride silicon is deposited in the range of 280-400° C. and 5-40 minute.
More concretely, a metal layer including aluminum-based material is deposited and patterned on an insulating substrate to form a gate wire including a gate line, a gate electrode connected to the gate line and a gate pad connected to the gate line, and a gate insulating layer is deposited. A semiconductor layer is formed, and a conductive layer is deposited thereon and patterned to form a data wire including a data line intersecting the gate line, a source electrode connected to the data line and adjacent to the gate electrode and a drain electrode opposite of the source electrode with respect to the gate electrode. Next, a passivation layer is deposited and patterned along with the gate insulating layer to form a first contact hole exposing the gate pad. A conductive layer pattern including a redundant gate pad connected to the gate pad through the first contact hole is formed on the passivation layer.
Here, it is desirable that the insulating layer and the passivation layer are deposited in the range of 280-400° C. and made of nitride silicon.
The conductive layer pattern may be indium zinc oxide.
The data wire further comprises a data pad connected to the data line, and a redundant data pad and a pixel electrode, which are respectively connected to the data pad and the drain electrode through a second and a third contact holes of the passivation layer, may be formed when forming the redundant gate pad.
The data wire and the semiconductor layer are together formed by photolithography process using a photoresist pattern having different thicknesses depending on the positions. The photoresist pattern may have a first portion having a first thickness, a second portion having a second thickness thicker than the first portion, and a third portion having a third thickness thinner than the first thickness and except for the first and the second portions.
A mask used for forming the photoresist pattern may have a first, a second, and a third part, a transmittance of the third part is higher than the first and the second parts, a transmittance of the first part is higher than the second part. The first and the second portion of the photoresist pattern may be respectively aligned on portion between the source electrode and the drain electrode, and the data wire.
It is desirable that the first part of the mask includes a partially transparent layer, or a slit pattern smaller than the resolution of the exposure used in the exposing step, to regulate the transmittance of the first part, and the thickness of the first portion is less than a half of the thickness of the second portion.
An ohmic contact layer may be formed between the data wire and the semiconductor layer, and the data wire, the ohmic contact layer, and the semiconductor layer may be formed in the same photolithography process.
REFERENCES:
patent: 5998230 (1999-12-01), Gee-Sung et al.
patent: 6287899 (2001-09-01), Park et al.
patent: 2001/0019125 (2001-09-01), Hong et al.
patent: 2002/0030190 (2002-03-01), Ohtani et al.
patent: 1998-079255 (1998-11-01), None
patent: 1999-0077818 (1999-10-01), None
Hur Myung-Koo
Kim Chi-Woo
Kong Hyang-Shik
McGuire Woods LLP
Tran Minh Loan
LandOfFree
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