Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-05-26
2003-02-04
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185110, C365S185220, C365S185280, C365S185290, C365S185210
Reexamination Certificate
active
06515905
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to an electrically erasable, rewritable nonvolatile semiconductor memory device (EEPROM) with testability, more particularly to a semiconductor memory device such as a flash memory with an automatic write or erase function.
2. Description of the Related Art
Flash memories have been in greatly increased demand in recent years due to non-volatility, easiness of erase and rewrite operations and adoption of single transistor cells.
A flash memory cell is of a stacked gate type in which a floating gate electrode is buried in the gate oxide film of a MOS transistor, and in a read operation, a high voltage is applied to the control gate while a voltage is applied between the drain and the source of the transistor to inject channel electrons into the floating gate electrode. With this electron injection, the threshold voltage of the transistor rises.
In the flash memory, an erase operation is required before a write operation. In the erase operation, a high voltage is applied to the source while leaving the drain in an open state to release electrons held in the floating electrode by a tunnel effect. When a memory cell is over-erased, erased, the floating gate in the memory cell is charged positive and thereby, a current flows between the source and the drain even if the control gate is set to OV, resulting in an erroneous read. In addition, there is variation in characteristics among the memory cells. Therefore, there is repeated the process of providing an erase pulse having a short width to a memory cell, performing a read operation on the memory cell and judging whether or not an erase operation has been performed properly. Also in a write operation, in order to prevent excessive write, there is repeated the process of providing a write pulse having a short width to the memory cell, performing a read operation on the memory cell and judging whether or not a write operation has been performed properly.
Such a repetition is performed automatically by a control circuit in a flash memory in response to an automatic write command or an automatic erase command, and when the repetition count exceeds a predetermined value before the operation of the automatic write or automatic erase has been completed, an error signal from the counter is activated to abnormally terminate the control operation.
However, if activation of the error signal is not transmitted to the control circuit when the number of the repetitions has exceeded the predetermined value because of a malfunction of the counter, or disconnection or short-circuiting of interconnection, the repetition is not terminated and it becomes an endless loop. Further, if no error cell is present, the excessive repetitions is not performed and therefore, a test cannot be performed on whether or not the error signal is issued normally.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a nonvolatile semiconductor memory in which it can be confirmed by adding a simple configuration whether or not an abnormally terminating operation is performed normally in a test prior to product shipment.
In the present invention, there is provided a nonvolatile semiconductor memory comprising a cell array, each cell having a floating gate; a sense amplifier for determining a logic value of a signal read from an addressed cell by comparing the signal with a reference signal; a counter for activating an error signal when a count thereof reaches a first predetermined value; and a control circuit, for repeating a write or erase operation on the addressed cell in response to an automatic write or erase command until the logic value reaches an expected value, for providing a counting signal to the counter at every repetition of the operation, for abnormally terminating the repetitions when the error signal has been activated, wherein the control circuit makes the counter load a second predetermined value for decreasing the number of the repetitions, prior to starting of the repetitions when a test signal is active.
With the present invention, the second predetermined value is loaded into the counter by activating the test signal in the test prior to product shipment, thereby it can be judged whether or not an error signal is outputted normally prior to a write or erase operation on a memory cell, or by smaller times of repetitions of write or erase operations. Accordingly the test can be performed with a shorter time and with certainty even if no error cell is present. Further, since in the test, the memory cell array receives no or less stress, a product lifetime will be extended.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.
REFERENCES:
patent: 5163021 (1992-11-01), Mehrotra et al.
patent: 5621687 (1997-04-01), Doller
patent: 5751647 (1998-05-01), O'Toole
Arent Fox Kintner & Plotkin & Kahn, PLLC
Ho Hoai
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