Method and system for halting processor execution in response to

Computer graphics processing and selective visual display system – Display driving control circuitry – Controlling the condition of display elements

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34518401, 34518306, 345838, 34580032, G06F 1130

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active

058752943

ABSTRACT:
A method and system within a data processing system are disclosed for halting execution of instructions by a processor in response to an enumerated occurrence of a selected combination of internal states within the processor. The processor includes a number of state machines and a means for monitoring the states of the number of state machines. According to the present invention, a selected combination of states of a subset of the state machines is specified. An enumerated occurrence of the selected combination of states of the subset of the state machines is then detected. In response to the enumerated occurrence of the selected combination of states, execution of instructions by the processor is halted such that states of the number of state machines within the processor remain substantially unchanged following the enumerated occurrence of the selected combination of states. In a first embodiment of the present invention, the selected combination of states is specified as a combination of states corresponding to an access to a specified address within an associated memory. According to a second embodiment of the present invention, the selected combination of states is specified as a selected sequence of states of a subset of the number of state machines.

REFERENCES:
patent: 3866184 (1975-02-01), Buhrke et al.
patent: 4231106 (1980-10-01), Heap et al.
patent: 4438490 (1984-03-01), Wilder, Jr.
patent: 4590550 (1986-05-01), Eilert et al.
patent: 4598364 (1986-07-01), Gum et al.
patent: 4821178 (1989-04-01), Levin et al.
patent: 4905171 (1990-02-01), Kiel et al.
patent: 5379390 (1995-01-01), Searing et al.
Harden et al., "A Performance Monitor for the MSPARC Multicomputer," IEEE, 1992, pp. 724-729.
Franklin et al., "POWER2: Performance Measurement and Analysis of TPC-C," IEEE, 1994, pp. 399-404.
Fineman et al., "Selective Monitoring Using Performance Metric Predicata," IEEE, 1992, pp. 162-165.
Krumme et al., "Integrated Debugging and Performance Monitoring for Parallel Programs," IEEE, 1991, pp. 317-318.
Lampp, Jr. et al., "Specification and Identification of Events for Debugging and Performance Monitoring of Distributed Multiprocessor Systems," IEEE, 1990, pp. 476-483.
IBM Technical Disclosure Bulletin, vol. 37, No. 04B, Apr. 1994, pp. 295-301.
IBM Technical Disclosure Bulletin, vol. 37, No. 09, Sep. 1994, pp. 465-467.
IBM Technical Disclosure Bulletin, vol. 24, No. 3, Aug. 1981, pp. 1416-1419.
IBM Technical Disclosure Bulletin, vol. 20, No. 8, Jan. 1978, pp. 3229-3230 .

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