On-chip histogram testing

Details On-chip histogram testing On-chip histogram testing

2001-03-23

2003-12-02

Assouad, Patrick (Department: 2857)

Data processing: measuring, calibrating, or testing

Measurement system

Statistical measurement

C702S106000, C341S120000

Reexamination Certificate

active

06658368

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to testing of integrated circuit components, and specifically to design-for-test (DFT) of analog and mixed-signal integrated circuits.
BACKGROUND OF THE INVENTION
Histogram testing is a well-known method for dynamic evaluation of analog-to-digital converter (ADC) devices. Typically, a sine wave of known frequency and amplitude is input to the ADC. The digital codes that are output by the ADC in response to the sine wave are recorded in a histogram, which is used to reveal both global characteristics and local errors of the device. For example, Peetz describes a number of uses of ADC histogram testing in an article entitled, “Dynamic Testing of Waveform Recorders,”
IEEE Transactions on Instrumentation and Measurement
IM-32:1 (March, 1983), pages 12-17, which is incorporated herein by reference. These uses include obtaining the differential nonlinearity of the ADC, determining whether any missing codes exist at the input test frequency, and measuring gain and offset at the test frequency. Wagdy et al. point out that histogram testing can also be used to determine the effective number of bits of the ADC, in “Determining ADC Effective Number of Bits Via Histogram Testing,”
IEEE Transactions on Instrumentation and Measurement
40:4 (August, 1991), pages 770-772, which is also incorporated herein by reference.
Modern, high-speed ADCs are designed to operate at frequencies in excess of 3 GHz. At these speeds, it is very difficult to collect histogram data using conventional off-chip test equipment. To address this problem, design-for-test (DFT) and built-in self test (BIST) techniques have been developed. These concepts are described generally by Vinnakota in
Analog and Mixed
-
Signal Test
(Prentice Hall PTR, Upper Saddle River, N.J., 1998), which is incorporated herein by reference. DFT techniques involve modifying a circuit on a chip to facilitate testing of the circuit, typically by improving fault coverage and/or making internal elements of the chip accessible for testing by external equipment. BIST also involves circuit modifications, but goes a step farther than DFT by actually embedding the test generator in the chip itself. Both DFT and BIST techniques generally require the addition of on-chip hardware, which is used only in the verification stage of chip development and is left thereafter as unused chip “real estate.”
Fluence Technology, Inc. (Beaverton, Oreg.), offers a histogram-based BIST system for on-chip testing, known as HABIST™. Aspects of this system are described in U.S. Pat. No. 5,793,642, whose disclosure is incorporated herein by reference. HABIST is intended particularly for use in testing high-performance ADCs. An analog test signal is generated by an on-chip source and is input to the ADC under test. A reference histogram, derived from either the test signal itself or from a simulation of the signal, is stored in a memory on chip. While the test signal is running, an on-chip histogram generator counts the occurrences of each of the possible output codes of the ADC and stores the results in a memory on the chip. It thus assembles the actual histogram of the ADC output. The reference histogram is subtracted from the actual histogram to give a variance histogram, which is then compressed, encoded and passed to an analyzer off chip in order to evaluate the circuit. It is sufficient for the link between the chip and the analyzer to operate at low speed, because both the high-speed test signal and the histogram are generated on chip, and only the encoded variance histogram need be passed to the analyzer. This convenience of operation is achieved, however, at the cost of substantial additional on-chip hardware, including analog circuits for generating the input test signal. Furthermore, the range of frequencies, amplitudes and waveform types that can be applied in the input signal to the ADC are limited to what the embedded analog test circuitry can offer.
SUMMARY OF THE INVENTION
Preferred embodiments of the present invention enable very high-speed histogram measurements to be made on analog integrated circuit components, without requiring analog test signal generation circuits on chip. A test waveform, typically a high-frequency sinusoid, is input to the chip under test from a standard signal generator via a suitable radio frequency (RF) probe. An ADC on the chip generates digital output codes responsive to the waveform. The ADC output is compared to a sequence of target codes using a simple on-chip comparator. Whenever the output code matches the target code, a “1” is output to a standard counter, which is connected to the chip by a second RF probe. By stepping the target code through the range of possible values of the output codes, and counting the matches for each code, a histogram of the ADC output is generated.
Thus, in preferred embodiments of the present invention, the ADC histogram is produced using substantially simpler on-chip test circuitry than what is required by BIST and DFT solutions known in the art. The histogram is generated and analyzed using standard, off-chip test equipment, with only a few RF probes connected to the chip itself for signal input and comparator readout. The histogram is analyzed by the off-chip equipment to determine characteristics of the analog components on the chip, and particularly of the ADC, such as the number of effective bits, differential nonlinearity and other properties, as mentioned in the Background of the Invention.
There is therefore provided, in accordance with a preferred embodiment of the present invention, circuitry for generating a histogram of output codes produced by an analog/digital converter (ADC) on an integrated circuit chip, the ADC producing the output codes at an output rate determined by a clock signal coupled to the ADC, responsive to an input signal applied to the ADC, the circuitry including:
a comparator, disposed on the chip together with the ADC, and including:
a first input coupled to receive the output codes from the ADC;
a second input coupled to receive a sequence of target codes covering at least a portion of a range of the output codes; and
an output, configured to assume a first state whenever the output and target codes are equal, and a second state when they are not equal; and
a pulse generator, disposed on the chip together with the ADC and the comparator, and coupled to receive the output of the comparator and, when the output is in the first state, to generate pulses for output from the chip at a pulse rate determined by the clock signal.
Preferably, the pulse rate is equal to the output rate of the ADC.
Further preferably, the circuitry includes a target code generator, which is coupled to apply each of the target codes in sequence to the second input of the comparator, so as to generate the histogram of the output codes. Preferably, the target code generator is arranged to apply each of the sequence of target codes to the comparator for a substantially equal number of cycles of the clock signal, during which the ADC receives the input signal and generates the output codes.
Additionally or alternatively, the pulse generator is arranged to convey the pulses to a probe applied to the chip, so as to carry the pulses to off-chip test equipment for counting the pulses and producing the histogram of the output codes.
There is also provided, in accordance with a preferred embodiment of the present invention, an integrated circuit chip, including:
an analog/digital converter (ADC), arranged to produce, responsive to an input signal applied to the ADC, a range of digital output codes at an output rate determined by a clock signal coupled to the ADC;
a comparator, including a first input coupled to receive the output codes from the ADC, a second input coupled to receive a sequence of target codes covering at least a portion of the range of the output codes, and an output, configured to assume a first state whenever the output and target codes are equal, and a second state when they are not equal; and
a pulse generator,

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