Modification to fill layers for inlaying semiconductor patterns

Details Modification to fill layers for inlaying semiconductor patterns Modification to fill layers for inlaying semiconductor patterns

2000-10-31

2003-02-18

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

Reexamination Certificate

active

06521537

ABSTRACT:

BACKGROUND
1. Field of Invention
This invention relates to the fabrication of semiconductor devices. More particularly, it relates to the use of the chemical mechanical polishing (CMP) process for preparing inlaid patterns. The invention involves modifications to the fill layers which result in changed polish rates, which are used to provide improved topography control of the surface during polish and potentially a lower product reject rate.
2. Description of the Related Art
In the fabrication of semiconductor devices, silicon (Si) wafers undergo numerous process steps involving pattern definition, etching, material deposition and excess material removal. Excess material removal is usually carried out by using chemical mechanical polishing (CMP) processes, which also controls the planarity of the wafer surface. Thus far CMP has focused on the rate of material removal, the selectivity ratios between components on a surface being polished, and planarizing capability. The planarization capability may be unique to the CMP process. It should be noted that “planarization” is considered on several levels, e.g. wafer-scale, die-scale and feature-scale.
An example of planarization on a feature scale is shown in
FIG. 1
, showing the evolution of the trench structure
2
′ topography as it is being planarized by CMP. The trenches
4
′ in this example are 0.6 m deep and representative of a polish using a Rodel IC1000 polisher at 2 psi polish pressure. Initially, the pad will not reach down in the trenches
4
′ and since there is no contact, and therefore no pressure applied to these down-features, only the up-features
6
′ are polished in levels I and II. When level III is reached, the polish pad contacts the down-features
4
′ and thus the point is reached where the surface is being planarized. The up-features
6
′ are in relief and are polished at a higher removal rate than the down features
4
′. The fill deposit is usually made sufficiently thick to allow planarization to take place when level IV is reached, as shown in FIG.
1
.
There are numerous variations of CMP processing steps during the manufacturing of IC devices on a silicon wafer. Some of these involve inlaying of materials. Examples of these include inlaying a pattern on the device surface of the Si wafer itself, such as where an oxide or another dielectric is inlaid in shallow trenches. Excess dielectric is usually removed by a CMP process for shallow trench isolation (STI). Later on in the device fabrication, patterns of W (tungsten) vias may be inlaid in a dielectric layer where excess W is removed by a CMP process developed for W. Other conductors such as Cu (copper), Al (aluminum), Ag (silver) and Au (gold) can be inlaid in dielectric layers by damascene or dual-damascene processes. There are usually several metallization layers, each requiring a CMP step. Excess metal can be removed by CMP processes tailored for the particular metal in question.
FIGS. 2 and 3
illustrate schematically a simple two-trench line structure having up- and down-features
8
′,
10
′ representative of real structures on a device. After pattern definition to form the trenches using, e.g. photolithography and etching of the substrate layer, a fill layer
12
′ is deposited on top of the substrate
15
′. Prior to deposition of the fill material, one or more intermediate layers
14
′ may or may not be deposited, this is shown schematically in
FIG. 2A
with the structure having an optional intermediate layer
14
′. For the purpose of simplification, the optional intermediate layer(s) will be omitted from the sketches in the following discussion, although in all cases they may or may not be present. Fill deposition is usually done using a conformal deposition
12
′ as shown in FIG.
2
B. However, regardless of initial topography, the CMP process planarizes the surface initially prior to pattern clearing as shown in FIG.
3
A. Assuming completely uniform removal, the CMP process produces the planar surface
16
′ of FIG.
3
B. Further polishing, to produce a structure shown in
FIG. 3C
, poses issues. In practice, due to polish non-uniformity and thickness variations at the outset of polishing, dies and structures are cleared at different polish times, and as a consequence some overpolish cannot be avpided, as shown in
FIG. 3D
where the fill deposit
12
′ in down-features
10
′ is depressed relative to the substrate, as a result. Overpolish may also be needed to ensure that the up-features of the substrate layer are totally free of fill-material residues. Assuming a high-selectivity slurry, where the polish rate of the substrate is negligible in comparison to that of the fill material, there is a strong tendency for dishing within the pattern fill, as shown in FIG.
3
D. To the degree that the substrate layer is polished, this removal manifests itself as erosion. When the fill polish rate is the highest, very thin substrate features are particularly prone to erosion due to the force concentration. It is desirable to minimize dishing and erosion after each polish and to obtain as near planar a surface as possible.
It has been an assumption in the description of the CMP process in the above description, that the initial topography is completely planar. However, in situations where the fill thickness is insufficient to reach planarazation, the areas above the up-features of the substrate, layer clear last—this can also be seen from FIG.
1
. Even when fill layers are thick, it is known in the art of CMP that some structures are particularly prone to clearing ahead of the field. This has a deleterious effect and increases erosion and dishing.
Most of the present effort to reduce dishing and erosion is focused on process optimization and slurry development, and in some cases costly multi-step and/or multi-slurry solutions have been attempted.
SUMMARY OF THE INVENTION
This summary of invention section is intended to introduce the reader to aspects of the invention and is not a complete description of the invention. Particular aspects of the invention are pointed out in other sections hereinbelow, and the invention is set forth in the appended claims which alone demarcate its scope.
The invention provides a method of fabricating semiconductor chips that includes modifying physical properties of selected deposited patterns to enhance chemical mechanical polishing (CMP), or other polishing, of these patterns without substantially affecting the electrical properties of the final semiconductor chip product. The invention also provides products of the method.
Briefly, in accordance with one aspect of the method of the invention, a modified pattern in the form of a film or layer is deposited on a pattern on a semiconductor wafer that has up- and down-features. The layer is modified through one of several techniques, including inclusion of an additive (another chemical species or alloying composition), stress relieving, or altering of the crystalline structure in order to selectively enhance the removal rate of at least a portion of the layer through chemical mechanical polishing, or other polishing. The selective enhancement of removal rate is particularly important in the damascene and dual-damascene processes, and reduces “dishing” commonly encountered during polishing such layers. Moreover, the removal rate enhancement potentially permits shorter polishing times, and as a consequence, higher chip manufacturing rates.
The invention also provides a semiconductor chip that includes layered microstructures that form electrical circuit(s). At least some of the microstructures include an inlaid composition that has been modified, by chemical additive doping, alloying, stress relieving, or crystalline alteration to alter selectively its polish removal rate in the fabrication stages.


REFERENCES:
patent: 5356513 (1994-10-01), Burke et al.
patent: 5510652 (1996-04-01), Burke et al.
patent: 5618381 (1997-04-01), Doan et al.
patent: 5681423 (1997-10-01), Sandhu et al

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