Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

1992-04-07

1993-12-21

Heyman, John S.

Excavating

371 682, 371 71, 370 15, G06F 1100, H04L 114

Patent

active

052727050

ABSTRACT:
A P-to-S shift register (61) includes nine R-S-FFs (70-78) serially connected. At the H level rising edge of a P-to-S shift register clock (T2), latch data of the FFs (70-77) are shifted rightwardly to their adjacent FFs (71-78), whereby a serial data (D1) from the FF (78) is outputted to a PWM portion and is transferred in a looped manner to the FF (70). Based on a delay time generated between the serial data (D1) and a demodulated serial data (D5), a comparator (63) compares the Q output (Q70) of the FF (70) in the P-to-S shift register (61) with the Q output (Q80) of the FF (80) in the S-to-P shift register (62) to output an echo back data (D9) based on a comparison result.
The necessity for providing a comparison portion (53) with specialized registers is eliminated, so that the chip size can be reduced.

REFERENCES:
patent: 3743938 (1973-07-01), Davis
patent: 4456997 (1984-06-01), Spitza
patent: 4864531 (1989-09-01), Quatse et al.
patent: 5060226 (1991-10-01), Gewin et al.

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