Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material
Reexamination Certificate
2000-08-17
2003-12-09
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
C438S622000, C438S645000, C438S699000
Reexamination Certificate
active
06660618
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the formation of high-density, multi-layer metallization semiconductor devices with reduced vertical capacitance variation. The invention has particular applicability in the manufacture of high-density, multi-layer metallization semiconductor devices with design features in the deep submicron range, such as 0.18 &mgr;m and below, e.g., 0.15 &mgr;m and below.
BACKGROUND OF THE INVENTION
The present invention relates to a method for forming semiconductor devices comprising multi-layer metallization systems with reduced vertical capacitance variation, and multi-layer metallization semiconductor devices obtained thereby, such as, for example, devices including clock skew circuits which must have very small variation in capacitance in order to avoid a racing condition. The present invention is especially adapted for use in semiconductor device manufacturing processing employing “damascene” (or “in-laid”) technology.
The escalating requirements for high density and performance associated with ultra-large scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing submicron-dimensioned (such as 0.18 &mgr;m and below, e.g., 0.15 &mgr;m and below), low resistance-capacitance (RC) time constant metallization patterns, particularly when the submicron-dimensioned metallization features, such as vias, contact areas, grooves, trenches, etc., have high aspect (i.e., depth-to-width) ratios due to microminiaturization.
Semiconductor devices of the type contemplated herein typically comprise a semiconductor wafer substrate, usually of doped monocrystalline silicon (Si), and a plurality of sequentially formed interlayer dielectrics and conductive patterns formed therein and/or therebetween. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by interwiring spacings and a plurality of interconnect lines, such as bus lines, bit lines, word lines, and logic interconnect lines. Typically, the conductive patterns of vertically spaced-apart metallization layers are electrically connected by a vertically oriented conductive plug filling a via hole formed in the inter-layer dielectric layer separating the layers, while another conductive plug filling a contact area hole establishes electrical contact with an active device region, such as a source/drain region, formed in or on the semiconductor substrate. Conductive lines formed in groove- or trench-like openings in overlying inter-layer dielectrics extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type fabricated according to current technology may comprise five or more layers of such metallization in order to satisfy device geometry and miniaturization requirements.
As device geometries shrink and the number of metallization levels increases, it has become increasingly important to reduce and/or stabilize the resistance-capacitance (“RC”) time constant of multi-level metallization systems at a particular value. Lower RC time constants are typically obtained by replacing typical silicon dioxide (SiO
2
)-based dielectrics having high dielectric constants (i.e., above about 3.9) with low dielectric constant (“low k”) materials having dielectric constants below 3.9, such as, inter alia, hydrogen silsesquioxane (HSQ), benzocyclobutene (BCB), polytetrafluoroethylene (TEFLON™), parylene, and polyimide. However, variation of inter-layer dielectric (ILD) thickness can result in significant variation in the capacitance between vertically separated metallization levels, thereby disadvantageously resulting in a variation of RC time constant which can cause a racing condition to occur in devices including clock skew circuitry. The variation in vertical capacitance between overlying metallization levels is particularly troublesome when the above-mentioned low k materials are employed as gap fill between metallization features having different linewidths and inter-line spacings because the spin-on coating techniques typically employed for their application cannot provide the required degree of thickness uniformity for minimum vertical capacitance variation over the lateral extent of the device substrate.
Referring now to
FIG. 1
, shown therein for facilitating an understanding of the present invention, is a very schematic sectional view through a semiconductor device having a ground plane
5
disposed substantially parallel to metal interconnect lines
1
-
4
. Electrical signals carried by each of interconnect lines
1
-
4
are affected by the RC time constant of that particular line. In the case of line
1
, the capacitance element of the RC time constant comprises four components: the first capacitance component C
12
is the line-to-line capacitance between lines
1
and
2
; the second capacitance component C
13
is the interlayer vertical capacitance between line
1
and vertically underlying line
3
; the third capacitance component C
14
is the interlayer diagonal capacitance between line
1
and diagonally underlying line
4
; and the fourth capacitance component C
15
is the line-to-ground capacitance between line
1
and ground
5
. Finally, C
11
is the total capacitance. While calculations indicate that the first, or line-to-line capacitance C
12
is the major component of the total capacitance C
11
, variation of C
12
can be minimized by use of high resolution, high precision pattern definition, masking, and etching techniques which provide substantially constant line widths and inter-line spacings. However, formation (e.g., as by spin-on deposition techniques of interlayer dielectric layers (ILDs) having highly uniform (i.e., constant) thickness over the wafer substrate surface is extremely difficult according to conventional practices. As a consequence, variation of the total capacitance C
11
due to variation of the interlayer vertical capacitance component C
13
and the interlayer diagonal capacitance component C
14
because of such thickness variation of the various interlayer dielectric layers is problematic in the manufacture of multi-level metallization semiconductor devices, resulting in excessive variation in device speed, creation of racing conditions in certain clock skew circuits, reduced product quality, and low manufacturing yield.
Another difficulty or drawback associated with the trend towards reduction of conductive wirings and interwiring spacings to the deep submicron range (i.e., 0.18 &mgr;m and below) stems from the inability to satisfactorily fill the interwiring spacings voidlessly and obtain adequate step coverage. It has also become very difficult to form reliable interconnection structures. In forming a conventional via, a through-hole is typically formed in a dielectric layer to expose an underlying metal feature, wherein the metal feature serves as a “landing pad” occupying the entire bottom of the through-hole. Upon filling the through-hole with conductive material, such as a metal plug forming a conductive via, the entire bottom surface of the conductive via plug is in direct contact with the metal feature.
A conventional fully bordered via, such as described above, is schematically illustrated in cross-section in
FIG. 2
, wherein first metal feature
10
of a first patterned metal layer is formed on first dielectric layer
11
and exposed by through-hole
12
formed in second dielectric layer
13
. First metal feature
10
comprises side surfaces which taper somewhat due to the etching process employed for their definition. In accordance with conventional practices, through-hole
12
is formed so that first metal feature
10
encloses the entire area of the opening at its bottom, thereby serving as a landing pad for the metal plug filling through-hole
12
for forming the conductive via. Thus, the entire bottom surface of conductive via plug
16
is in direct contact with the upper surface of the first metal feature
10
. Conductive via plug
16
electrically connects first metal feature
10
and second metal feature
14
which is
Besser Paul R.
Chen Susan H.
Advanced Micro Devices , Inc.
Rocchegiani Renzo N
Smith Matthew
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