Methods of forming bipolar transistor constructions

Details Methods of forming bipolar transistor constructions Methods of forming bipolar transistor constructions

2002-03-08

2003-02-25

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

C438S338000, C438S342000

Reexamination Certificate

active

06524921

ABSTRACT:

TECHNICAL FIELD
The invention pertains to bipolar transistor constructions, and to methods of forming bipolar transistor constructions.
BACKGROUND OF THE INVENTION
Bipolar transistor constructions can have numerous applications in modern semiconductor devices. For instance, bipolar transistors can be incorporated into electrostatic discharge (ESD) protection schemes for complementary metal oxide semiconductor (CMOS) assemblies. An exemplary CMOS assembly is described with reference to
FIG. 1
, which illustrates a fragment of a semiconductor wafer
10
.
Wafer
10
comprises a substrate
12
. Substrate
12
can comprise, consist essentially of, or consist of monocrystalline silicon lightly doped with a background p-type dopant (so-called p-minus, or p−, doping). To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
An exemplary background p-type dopant concentration within substrate
12
is less than 1×10
16
atoms/cm
3
; such as, for example, from about 1×10
14
atoms/cm
3
to about 1×10
16
atoms/cm
3
. A suitable p-type dopant is boron.
A plurality of n-wells
14
,
16
and
18
are formed within substrate
12
by implanting a suitable n-type dopant (such as, for example, phosphorous or arsenic) into substrate
12
. The concentration of n-type dopant within n-wells
14
,
16
and
18
is preferably at least 10-fold higher than the background concentration of p-type dopant within substrate
12
, and accordingly overwhelms the p-type dopant within regions
14
,
16
and
18
. A suitable concentration of n-type dopant is from about 1×10
15
atoms/cm
3
to about 1×10
18
atoms/cm
3
.
A plurality of isolation regions
20
are formed across an upper surface of substrate
12
. Isolation regions
20
can comprise, for example, shallow trench isolation regions filled with an appropriate insulative material, such as silicon dioxide.
A plurality of p-type metal oxide semiconductor (PMOS) transistor structures
22
are formed to be supported by substrate
12
, and to be associated with n-well regions
14
,
16
and
18
. Also, a plurality of n-type metal oxide semiconductor (NMOS) transistor constructions
24
are formed to extend across substrate
12
and to be associated with p-type regions between the n-wells. PMOS transistors
22
comprise source/drain regions
26
which are doped with an appropriate p-type dopant, and NMOS transistors
24
comprise source/drain regions
28
which are doped with an appropriate n-type dopant. NMOS transistors
22
and PMOS transistors
24
comprise transistor gate structures
30
and sidewall spacers
32
along the transistor gates. Transistor gates
30
can comprise, for example, a layer of gate oxide and overlying layers of conductive materials (such as, for example, one or more of conductively-doped silicon, metal and metal silicide). Sidewalls
32
can comprise, for example, silicon nitride or silicon dioxide. The transistor gates associated with NMOS constructions
24
can be different than those associated with PMOS constructions
22
. For instance, the gates associated with the NMOS constructions can comprise n-type conductively doped polycrystalline silicon, while the gates associated with the PMOS constructions can comprise p-type conductively doped polycrystalline silicon.
It would be desirable to develop bipolar transistor constructions which can be readily incorporated into CMOS assemblies of the type described with reference to FIG.
1
.
SUMMARY OF THE INVENTION
In one aspect, the invention encompasses a bipolar transistor construction having a collector region, emitter region, and base region extending within a semiconductive material substrate. The construction further comprises separate access regions associated with the base region, emitter region and collector region, respectively. An n-type doped connecting region is comprised by the collector region and extends beneath the emitter and base regions. A p-type doped location is comprised by the base region and extends beneath the emitter region and above the n-type doped connecting region. An n-type doped intermediate location is within the emitter region and between the p-type doped location and the emitter access region.
In other aspects, the invention encompasses methods of forming bipolar transistor constructions.


REFERENCES:
patent: 4007474 (1977-02-01), Yagi et al.
patent: 5504018 (1996-04-01), Sato
Silicon Processing for the VLSI Era—vol. II; pp. 482-483.
“ESD Protection Scheme using CMOS Compatible Vertical Bipolar Transsitor for 130 nm CMOS generation”; Mototsugu Okushima et al; IEEE; 2000; pp. IEDM 00-127-00130.

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