Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2001-05-25
2003-12-02
Talbott, David L. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S776000, C257S210000, C257S691000, C257S208000
Reexamination Certificate
active
06657307
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor integrated circuit having a functional macro with an improved power line connection structure.
2. Description of the Related Art
FIG. 1
is a schematic view of a structure of a memory macro that is an example of a functional macro. A functional macro
1
comprises an address decode block
10
, a memory cell block
11
, an address block
12
and a data input/output block
13
. The blocks
10
,
11
,
12
and
13
are optimized so as to minimize the area of the functional macro
1
.
FIG. 2
is a schematic view of layout of power supply lines of functional macro
1
. Power supply lines
2
are provided in random over the functional macro
1
. The power supply lines
2
typically are third level interconnections. First and second level interconnections are not illustrated in FIG.
2
.
FIG. 3
is a plan view of a semiconductor integrated circuit that includes the functional macro of FIG.
1
. The functional macro
1
is placed on a region of a semiconductor integrated circuit
4
, that has a regular alignment of power source lines
5
, which may be fifth level interconnections.
FIG. 4
is a fragmentary enlarged plan view of a region “A” defined by a broken line in FIG.
3
. The power lines
5
of the semiconductor integrated circuit
4
have a different alignment from the power lines
2
of the functional macro
1
. When the functional macro
1
is placed on the semiconductor integrated circuit
4
, the power lines
5
of the semiconductor integrated circuit
4
may partially overlap the power lines
2
of the functional macro
1
. Only the overlapping power lines
5
are electrically connected to the power lines
2
. In
FIG. 4
, the overlapping power line
5
is marked by a broken line region “B”. This alignment scheme makes it difficult to supply sufficient power to the functional macro
1
.
FIG. 5
is a fragmentary enlarged plan view of a center region “A” of another semiconductor integrated circuit. Adjacent power lines
2
and
5
are electrically connected to each other through additional power lines
6
. The width of each of the additional power lines
6
is determined in consideration of an allowable low voltage. Variation of placement conditions causes variation of connection conditions. It is necessary for designers to calculate separately the width of each additional power line
6
since the placement conditions vary. This additional design work is inconvenient and undesirable.
FIG. 6
is a fragmentary enlarged plan view of a center region “A” of still another semiconductor integrated circuit. The power lines
2
of the functional macro
2
are aligned with the power lines
5
of the semiconductor integrated circuit
4
. Thus, the alignment of the power lines
2
is based on the alignment of the power lines
5
. This increases the area of the functional macro
1
.
In the above circumstances, the development of a novel semiconductor integrated circuit having a functional macro free from the above problems is desirable.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a novel semiconductor integrated circuit (IC) having a functional macro that is connected to the power lines for the IC in a manner that avoid the problems of the prior art.
It is a further object of the invention to provide a novel IC having a functional macro that is connected to the power lines for the IC with a structure that includes power terminal patterns on a level between the levels of the power lines for the IC and the power lines for the function macro where each of the power terminal patterns extends between a first area corresponding to an adjacent pair of the macro power lines and a second area corresponding to an adjacent pair of the IC power lines.
It is a another object of the invention to provide a novel IC having a functional macro that is connected to the power lines for the IC with a structure that includes power terminal patterns on a level between the levels of the power lines for the IC and the power lines for the function macro where each of the power terminal patterns has the same size and shape.
It is yet another object of the invention to provide a novel IC having a functional macro that is connected to the power lines for the IC with a structure that includes power terminal patterns on a level between the levels of the power lines for the IC and the power lines for the function macro where the power terminal patterns includes a repeating pattern of similar shapes that are spaced the same distance from each other.
These objects and other objects, features, and advantages of the present invention will be apparent from the following description of preferred embodiments.
REFERENCES:
patent: 4989062 (1991-01-01), Takahashi et al.
patent: 5095352 (1992-03-01), Noda et al.
patent: 5850091 (1998-12-01), Li et al.
patent: 6269466 (2001-07-01), Crafts
patent: 6326693 (2001-12-01), Mimoto et al.
patent: 2180050 (1990-07-01), None
patent: 4033367 (1992-02-01), None
patent: 4302161 (1992-10-01), None
patent: 5083189 (1993-04-01), None
patent: 6291256 (1994-10-01), None
NEC Electronics Corporation
Young & Thompson
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