Semiconductor memory with improved sense amplifier layout

Details Semiconductor memory with improved sense amplifier layout Semiconductor memory with improved sense amplifier layout

1992-06-24

1993-12-21

LaRoche, Eugene R.

Static information storage and retrieval

Interconnection arrangements

36518901, 365207, 365208, G11C 1300

Patent

active

052726657

ABSTRACT:
A semiconductor memory has a matrix of memory cells crossed by word lines and bit lines. In each group of eight adjacent bit lines, a first sense amplifier is coupled to the first and sixth bit lines, a second sense amplifier to the third and eighth bit lines, a third sense amplifier to the second and fifth bit lines, and a fourth sense amplifier to the fourth and seventh bit lines. The first and third sense amplifiers are located side by side on one side of the memory matrix, between the second and fifth bit lines. The second and fourth sense amplifiers are located side by side on the opposite side of the memory matrix, between the fourth and seventh bit lines.

REFERENCES:
patent: 4920517 (1990-04-01), Yamauchi et al.
patent: 4982368 (1991-02-01), Arimoto

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