Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-10-20
2003-02-25
Goudreau, George (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S725000, C438S696000, C438S700000, C134S001200, C216S067000
Reexamination Certificate
active
06524963
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to the etching of organic-based, low dielectric constant materials in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
With the continuing reduction in the feature size in the art of semiconductor manufacture, conductive traces and active devices are now fabricated very closely together. This greater proximity has led to the tremendous packing densities of modern ultra large-scale integration (ULSI). With these greater densities and closer device spacings has come the problem of greater capacitive coupling between adjacent circuit elements.
Traditionally, circuit elements have been electrically isolated primarily through the use of silicon dioxide. Silicon dioxide is well-known in the art as a fundamental building block in integrated circuit manufacture. It is easy to form through thermal oxidation of silicon or by various deposition methods. Silicon dioxide is also easy to reliably etch through both wet and dry chemistry.
Unfortunately, the dielectric constant of silicon dioxide is relatively high. This is an advantage when silicon dioxide is used, for example, as a gate dielectric. It is a disadvantage, however, when silicon dioxide is used to isolate, for example, adjacent metal conductors. In this application, the relatively high dielectric constant of the silicon dioxide can cause significant capacitive coupling between the metal lines. This problem is especially pronounced in modern ULSI circuits, where metal lines are formed with very small spaces between them. Often, these lines run relatively long distances in parallel (as data or address buses, for example). The capacitive coupling can cause problems with high-speed operation and with data errors due to cross talk between the conductors.
To reduce the capacitive coupling between elements in the circuit, while still achieving the essential electrical isolation, new dielectric materials have been developed and introduced into integrated circuit manufacturing. These new materials typically are based on organic compounds that may also contain inorganic elements, such as silicon. For example, spin-on-glass (SOG) materials, such as silsesquioxane have been introduced. Amorphous carbon dielectric materials and organic polymers have also been applied in place of silicon dioxide. These new materials reduce the dielectric constant of the insulating layer formed, thus improving circuit performance.
There are many difficulties to overcome in using these new materials, however. One problem of particular concern is etching. Traditional methods and chemistries used for etching these new materials encounter problems as will be seen in the prior art example.
Referring to
FIG. 1
, a cross-section of a partially completed prior art integrated circuit device is shown. In this example, a damascene via is being formed. A semiconductor substrate
10
is shown. The semiconductor substrate
10
could be composed of silicon or of several microelectronics layers such as insulator layers and conductor layers. Metal traces
18
are formed in a first insulating layer
14
overlying the semiconductor substrate
10
. A second insulating layer
22
, typically of silicon nitride, overlies and isolates the metal traces
18
. A low dielectric constant material
26
comprised of an organic-based material is applied overlying the second insulating layer
22
. Finally, a polishing stop layer
30
, typically comprised of silicon nitride, overlies the low dielectric constant material
26
. In this example, the trench to create a damascene via to contact the metal traces
18
will be constructed.
Referring now to
FIG. 2
, a photoresist layer
32
overlies the polishing stop layer
30
. The photoresist layer
32
is patterned to form openings where trench vias are planned. The polishing stop layer
30
is so named because it will stop the polishing operation used to define the subsequently deposited metal material to the confines of the damascene trench. Here, the polishing stop layer
30
will also act as a hard mask for etching the low dielectric constant material
26
.
Referring now to
FIG. 3
, the polishing stop layer
30
and the low dielectric constant material
26
are etched. The polishing stop layer is etched using fluorocarbon chemistry. Typically, the etching of the organic low dielectric constant material
26
is performed using an oxygen plasma chemistry. The typical reaction for such an etch is given by:
C
x
H
y
N
z
+O
2
→CO
2
+H
2
O+NO
x
.
Oxygen etching has the advantage of generating and depositing little polymer onto the sidewalls of the etched feature. Unfortunately, the etching profile is difficult to control and over etching
34
, sometimes called bowing, is often seen. These results can lead to loss of device yield, as well as reliability problems, through the creation of voids and device shorts.
A second technique used to etch the low dielectric constant material
26
uses a plasma containing hydrogen gas and nitrogen gas. The use of hydrogen to reduce, rather than to oxidize the material, improves the etching control. The profiles produced by this type of etch chemistry are better than those produced using an oxygen chemistry. The hydrogen reaction is typically shown as:
C
x
H
y
N
z
+H
2
→CH
x
+NH
x
+H
2
.
The main problem with the hydrogen and nitrogen chemistry is one of safety. Hydrogen is highly flammable. Any inadvertent introduction of oxygen into the etching chamber can lead to an explosion. In addition, because both hydrogen and nitrogen gas are separately ported to the reaction chamber, separate utilities, including mass flow controllers (MFC) must be used.
Several prior art approaches disclose methods to etch low dielectric constant materials as well as uses of hydrazine compounds in the fabrication of integrated circuits. U.S. Pat. No. 5,232,872 to Ohba teaches a process to form conductive connections on a semiconductor substrate by using N
2
H
4
(hydrazine) and related compounds to clean contact openings and to catalyze deposition of metals from metal complexes. U.S. Pat. No. 5,728,259 to Suzawsa et al discloses a process to etch silicon thin films using liquid hydrazine. U.S. Pat. No. 5,888,309 to Yu teaches a method to etch various low dielectric constant materials where first a fluorine containing plasma is used to etch an opening. Next, an oxygen plasma is used to remove the photoresist patterned layer and to partially etch the polymer formed in the opening by the fluorine etch. Finally, the polymer is removed by a wet chemical strip. U.S. Pat. No. 5,759,906 to Lou shows a planarization process for low dielectric constant materials. U.S. Pat. No. 5,888,905 to Taylor et al discloses a polymer formation and etchback method to form a low dielectric constant material on an integrated circuit.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of etching organic-based, low dielectric constant materials in the manufacture of integrated circuits.
A further object of the present invention is to provide a method to etch organic-based, low dielectric constant materials that improves the etching control and profile by using a plasma containing a gas comprising a nitrogen and hydrogen containing molecule.
A yet further object of the present invention is to provide a method to etch organic-based, low dielectric constant materials that eliminates potential safety problems associated with the use of hydrogen gas by using a plasma containing a gas comprising a nitrogen and hydrogen containing molecule.
Another yet another further object of the present invention is to provide a method to etch organic-based, low dielectric constant materials that requires only one etching gas by using a plasma containing a gas comprising a nitrogen and hydrogen containing molecule.
Another yet further object of the present invention is to provide a method
Chooi Simon
Li Jian Xun
Zhou Mei Sheng
Chartered Semiconductor Manufacturing Ltd.
Goudreau George
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