Variable frequency divider circuit

Details Variable frequency divider circuit Variable frequency divider circuit

2001-09-24

2003-02-18

Wambach, Margaret R. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

C377S047000

Reexamination Certificate

active

06522711

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a variable frequency divider circuit, and in particular, to a structure of a variable frequency divider circuit capable of changing its division ratio between F and F+1 with F being a natural number. Specifically, the present invention relates to a high-speed frequency divider (prescaler) circuit formed through. CMOS process.
2. Description of the Background Art
In recent years, the miniaturization of components in the CMOS (complementary metal-insulating film-semiconductor) process is progressed, to make it possible to manufacture a circuit for processing RF (radio frequency) band signals, which operates at a GHz (giga-hertz) speed, such as a PLL (phase locked loop) synthesizer.
FIG. 13
is a diagram representing a conventional high-speed frequency divider.
FIG. 13
shows, as one example of high-speed frequency dividers, the structure of a prescaler in which its frequency division ratio can be changed between 1/4 and 1/5. When the frequency division ratio of the prescaler is 1/F, the frequency of the output signal thereof is 1/F times that of an input signal.
In
FIG. 13
, the prescaler includes three cascaded flip-flops
1
-
3
. In the flip-flops
2
and
3
, their output signals FBA and FBB are fed back to the first stage flip-flop
1
. Complementary output signals OUT and OUTB are outputted through output terminals
9
and
10
from the first stage flip-flop
1
. Each of the flip-flops
1
-
3
performs transfer/latch operation of the feedback signals FBA and FBB in accordance with complementary input signals ZIN and IN applied to terminals
6
and
7
to generate frequency-divided signals OUT and OUTB of the input signals IN and ZIN.
The flip-flop
1
includes two cascaded latch circuits LT
1
and LT
2
performing transfer/latch operation complementarily to each other in accordance with the input signals IN and ZIN. The latch circuit LT
1
includes: resistance elements
11
a
and
11
b
, each connected, at one end thereof, connected to a power node; N channel MOS transistors
16
and
17
each having a drain connected to the other end of the resistance element
11
a
and a gate receiving the feedback signal FBB, FBA; and an N channel MOS transistor
18
having a drain connected to the resistance element
11
b
and having a gate receiving a reference voltage Vr supplied through a terminal
5
. The sources of these MOS transistors
16
-
18
are connected together.
The latch circuit LT
1
further includes: an N channel MOS transistor
12
having a drain connected to a common source node of the MOS transistors
16
-
18
, and a gate receiving the input signal IN supplied through a terminal
7
; an N channel MOS transistor
19
having a drain connected to the common drain node of the MOS transistors
16
and
17
, and a gate connected to the drain of the MOS transistor
18
; an N channel MOS transistor
20
having a drain connected to the drain of the MOS transistor
18
, a gate connected to the common drain node of the MOS transistors
16
and
17
, and a source connected to the source of the MOS transistors
19
; an N channel MOS transistor
13
having a drain connected to the common source node of the MOS transistors
19
and
20
, a source connected to the source of the MOS transistor
12
, and a gate receiving the complementary input signal ZIN supplied through a terminal
6
; and an N channel MOS transistor
4
connected between the common source node of the MOS transistors
12
and
13
and a ground node and having a gate receiving a constant voltage Vc supplied through a terminal
8
.
The MOS transistor
4
functions as a current source transistor and had its supplying current determined by the constant voltage Vc supplied to the gate thereof. The MOS transistors
12
and
13
conduct the current complementarily in accordance with the input signals IN and ZIN. The sources of the MOS transistors
16
-
18
are connected together, and a current flows through the MOS transistor receiving the highest gate voltage. The circuit.structure in which a MOS transistor receiving the highest gate voltage among MOS transistors having their sources connected together, flows substantially all the current as described above is referred to as a “source coupled logic” hereinafter.
The reference voltage Vr supplied to the MOS transistor
18
is set to a criterion voltage level for determining the H level and the L level of the feedback signals FBB and FBA supplied to the gates of the MOS transistors
16
and
17
, and is normally set to a middle voltage level between the H and L voltage levels.
The MOS transistors
19
and
20
constitute a “source coupled logic” when the MOS transistor
13
is made conductive, and latch the output signals of the MOS transistors
16
-
18
due to the structure that their gates and drains are cross-coupled.
Similarly to the latch circuit LT
1
, the latch circuit LT
2
includes: resistance elements
11
c
and
11
d
each having one end connected to the power node; an N channel MOS transistor
21
having a drain connected to the other end of the resistance element
11
c
and a gate connected to the drains of the MOS transistors
18
and
20
; an N channel MOS transistor
22
having a drain connected to the other end of the resistance element
11
d
, a gate connected to the drains of the MOS transistors
16
,
17
and
19
, and a source connected to the source of the MOS transistor
21
; an N channel MOS transistor
14
having a drain connected to the common source node of the MOS transistors
21
and
22
and a gate receiving the input signal ZIN applied from the terminal
6
; an N channel MOS transistor
23
having a drain connected to the drain of the MOS transistor
21
and a gate connected to the drains of the MOS transistors
22
and
24
; an N channel MOS transistor
24
having a drain connected to the drain of the MOS transistor
22
, a gate connected to the drains of the MOS transistors
21
and
23
, and a source connected to the source of the MOS transistor
23
; an N channel MOS transistor
15
having a drain connected to the common source node of the MOS transistors
23
and
24
, a source connected to the source of the MOS transistor
14
and a gate receiving the input signal IN; and a current source N channel MOS transistor
4
b
connected between the common source node of the MOS transistors
14
and
15
and the ground node and having a gate receiving the constant voltage Vc supplied through the terminal
8
.
MOS transistors
23
and
24
have their gates and drains cross-coupled, to latch output signals of the MOS transistors
21
and
22
when the MOS transistors
23
and
24
are active.
This latch circuit LT
2
takes in complementary output signals of the latch circuit LT
1
when the input signal ZIN is at an H level, and latches the complementary signals when the input signal IN turns into an H level. Accordingly, the latch circuit LT
2
transfers the output signals of the latch circuit LT
1
with delay of a half of one cycle of the input signal IN, to output the signals to the output terminals
9
and
10
.
The flip-flop
2
also includes two cascaded latch circuits LT
3
and LT
4
to perform transfer/latch operation complementarily to each other in response to the input signals IN and ZIN. The latch circuits LT
3
and LT
4
in this flip-flop
2
have the same structure as the latch circuit LT
2
. In accordance with the input signals IN and ZIN, the latch circuits LT
3
and LT
4
transfer and latch the complementary output signals (actual output signals OUT and OUTB of the frequency divider) of the latch circuit LT
2
.
The flip-flop
3
also includes latch circuits LT
5
and LT
6
to perform transfer/latch operation complementarily to each other in response to the input signals IN and ZIN. The latch circuits LT
5
has the same structure as the latch circuits LT
2
-LT
4
have. This latch circuit LT
5
takes in complementary output signals of the latch circuit LT
4
in the flip-flop
2
when the input signal ZIN is at an H level, and latches the comp

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