Demultiplexer for an isochronous multiplex signal

Details Demultiplexer for an isochronous multiplex signal Demultiplexer for an isochronous multiplex signal

1991-10-28

1994-01-04

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

328105, H04L 522, H04J 304

Patent

active

052766896

ABSTRACT:
A demultiplexer for an isochronous multiplex signal is described which signal consists of isochronous sub-signals interleaved block by block. The demultiplexer comprises a read-write memory (MXA, MXB, MXC, MXD) as well as a read-write control (ST). The proposed circuit arrangement may be devised in a highly advantageous manner as an integrated circuit because it is has been considered that, for example, the manufacturers of gate arrays leave the user only the choice of using building blocks depicted in a catalogue. These building blocks constitute the function blocks (MXA to MXD) which are provided for partitioning an STM-16 signal into four sub-signals (STM4A, STM4B, STM4C, STM4D). The control signals for these function blocks (TL15:0, Z(3:0), T311, T622) are produced by a control circuit (ST) whose central module is a four-stage cyclic counter. The necessary control signals are derived from the count of the cyclic counter by means of addressable demultiplexers.

REFERENCES:
patent: 4542503 (1985-09-01), Fladerer et al.
patent: 4949339 (1990-08-01), Shimada et al.
patent: 5150364 (1992-09-01), Negus
CCITT Recommendations G.707, G.708 and G.709.

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