Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal – Electromagnetic or particle radiation
Reexamination Certificate
2001-07-19
2003-06-24
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Responsive to non-electrical signal
Electromagnetic or particle radiation
C257S676000, C257S786000
Reexamination Certificate
active
06583483
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention pertains to a semiconductor device and a method of manufacturing such device that utilizes a conductive wire bonding technique, and specifically pertains to a semiconductor device and a method of manufacturing such device that is appropriate to the purpose of reducing the thickness of such device package.
CROSS-REFERENCES TO RELATED APPLICATIONS
(None)
BACKGROUND OF THE INVENTION
Prior Art
The widespread use of mobile computers and cellular telephones in recent years has accelerated the miniaturization and heightened functionality of these products, and as a result the need has arisen for the semiconductor devices installed in these products to be further miniaturized and heightened in functionality. These kind of demands on semiconductor devices increase the number of input/output channels per unit surface area as well as narrow the pitch between bonding pads on the internal semiconductor chip.
Generally, bonding pads on a semiconductor chip are located in a single row, lined up at the edges of the main surface of the semiconductor chip (known as in-line rows). However, if the pitch between bonding pads is narrowed as discussed above, when the conductive wire is to be bonded to the bonding pads, the tip of the capillary that supplies the wire comes into contact with the conductive wire on top of the neighboring bonding pad. At this point, in existing processes, so-called staggered rows, where neighboring bonding pads are located alternately on the inner side and outer side of the edge of the main surface of the semiconductor chip, have come to be employed in conjunction with the miniaturization and heightening in functionality of the above semiconductor chip.
On the other hand, in conductive wire bonding methods, there is also a technique known as reverse bonding, wherein opposite to ordinary bonding procedure, bonding is carried out first on the wiring and inner lead portions on the substrate to which the semiconductor chip is mounted (hereinafter “land”), and after that the end of the conductive wire is bonded to the bonding pad on the semiconductor chip. An advantage of reverse bonding is that it reduces the thickness of the semiconductor package, since reverse bonding does not require a protuberance of the conductive wire on top of the bonding pad.
Problem to be Solved by the Invention
However, a problem when employing reverse bonding is that the pitch between the bonding pads cannot be narrowed as much as it can when employing ordinary bonding. In other words, in reverse bonding, during the bonding process, the conductive wire is pressed down on the bonding pad, changing its shape, before the capillary is pulled up. As a result, after severing it, the edge of the conductive wire is fanned out in a semicircular shape extending beyond the region of the bonding pad, and there is a danger that this could come into contact with a neighboring conductive wire. This problem cannot be avoided even when using the above staggered rows as the positioning for the bonding pads.
Accordingly, an objective of this invention is to provide for a semiconductor device and a method of manufacturing such a semiconductor device that allows for reduction of the pitch between bonding pads similar to that obtainable when employing ordinary bonding, while utilizing a reverse bonding process.
SUMMARY OF THE INVENTION
This invention pertains to a semiconductor device that employs reverse bonding technique. A semiconductor device embodying this invention is comprised of a semiconductor chip comprised of multiple bonding pads located in staggered rows on its edges; a substrate mounted with the above semiconductor chip and comprised of multiple lands connected electrically to the above multiple bonding pads; a bump portion formed on top of a bonding pad as above that is located on the inner side of the above semiconductor chip; a first conductive wire wherein the beginning is connected to a land as above and the end is connected to a bonding pad as above that is located on the outer side of the above semiconductor chip; a second conductive wire wherein the beginning is connected to a land as above and the end is connected to a bump as above on a bonding pad as above located on the inner side of the above semiconductor chip; and resin affixing the above semiconductor chip, a first conductive wire as above, and a second conductive wire as above.
A semiconductor device embodying this invention is also comprised of a semiconductor chip comprised of multiple bonding pads located in staggered rows on its edges; multiple lands connected electrically to the above multiple bonding pads; a bump portion formed on top of a bonding pad as above that is located on the inner side of the above semiconductor chip; a first conductive wire wherein the beginning is connected to a land as above and the end is connected to a bonding pad as above that is located on the outer side of the above semiconductor chip; a second conductive wire wherein the beginning is connected to a land as above and the end is connected to a bump as above on a bonding pad as above located on the inner side of the above semiconductor chip; and resin affixing the above semiconductor chip, a first conductive wire as above, and a second conductive wire as above.
The above semiconductor device may be further equipped with a second semiconductor chip, and the above land may be comprised of bonding pads formed on top of the other semiconductor chip. Also, the above semiconductor device may be further equipped with a lead frame, and the above land may be formed on the inner lead portion of the lead frame.
In the semiconductor device discussed above, it is preferable that the above bump portion on a bonding pad as above located on the inner side of the above semiconductor chip is a stud bump stack that stacks two or more stud bumps. Also, it is preferable that the height of the above bump portion be 60 microns or more from the front surface of the above semiconductor chip.
This invention also provides for other semiconductor devices that employ reverse bonding technique. Such semiconductor devices are comprised of a semiconductor chip comprised of multiple bonding pads located in staggered rows on its edges; a substrate mounted with the above semiconductor chip and comprised of multiple lands connected electrically to the above multiple bonding pads; a first conductive wire wherein the beginning is connected to a land as above and the end is connected to a bonding pad as above that is located on the outer side of the above semiconductor chip; a second conductive wire wherein the beginning is connected to a bonding pad as above located on the inner side of the above semiconductor chip and the end is connected to a land as above; and resin affixing the above semiconductor chip, a first conductive wire as above, and a second conductive wire as above.
This invention also provides for a method of manufacturing semiconductor devices that employ reverse bonding technique. A method for manufacturing a semiconductor device pertaining to this invention is comprised of a process for affixing a semiconductor chip comprised of multiple bonding pads located in staggered rows on its edges onto an insulated substrate comprised of multiple lands connected electrically to the above multiple bonding pads; a process for forming a bump portion on top of a bonding pad as above located on the inner side of the above semiconductor chip; a process for connecting a land as above with a bonding pad as above located on the outer side of the above semiconductor chip with a first conductive wire, with beginning at the above land and the end at the above bonding pad located on the outer side of the above semiconductor chip; a process for connecting a land as above with the above bump portion on a bonding pad as above located on the inner side of the above semiconductor chip, with the beginning at the above land and the end at the above bump portion of a bonding pad as above located on the inner side of the above semiconductor chip; and a p
Karashima Akira
Masumoto Kenji
Masumoto Mutsumi
Skrehot Michael K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Wade James Brady III
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