Semiconductor device

Details Semiconductor device Semiconductor device

2000-02-16

2003-06-17

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

Insulating coating

C257S637000, C257S643000, C257S760000

Reexamination Certificate

active

06580155

ABSTRACT:

RELATED APPLICATION DATA
The present application claims priority to Japanese Application No. P11-040335 filed Feb. 18, 1999 which application is incorporated herein by reference to the extent permitted by law.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same and, more particularly, a semiconductor device such as a semiconductor integrated circuit device having a structure in which at least two conductive layers such as wiring layers are stacked via an interlayer insulator and a method of fabricating the same.
2. Description of the Related Art
Since the components are becoming finer in association with the miniaturization of a semiconductor device, that is, the size according to what is called a device rule is becoming smaller, the distance between wiring patterns is shortened. For example, when neighboring wiring patterns in a lower wiring layer is narrowed, there is a problem of a parasitic capacity caused by an interlayer insulator interposed between the lower wiring layer and an upper wiring layer formed so as to enter the space between the neighboring wiring patterns. Attention is paid to a problem such as an operation delay caused by the parasitic capacity.
It is therefore becoming more and more necessary to examine an insulating material of a low dielectric constant as the insulating material of the interlayer insulator.
For instance, as shown in a schematic cross section of the main part in
FIG. 9
, a semiconductor integrated circuit device has a structure such that two or more layers such as a lower conductive layer
11
and an upper conductive layer
12
are stacked via an interlayer insulator
2
on a semiconductor substrate
1
.
In the example of the diagram, on an insulating layer
3
made of SiO
2
or the like deposited on the substrate
1
, the lower conductive layer
11
such as a lower wiring layer in a predetermined pattern made of a metal, a polycrystal semiconductor, or the like is formed. On the lower conductive layer
11
, the upper conductive layer
12
such as an upper wiring layer in a predetermined pattern made of a metal, a polycrystal semiconductor, or the like is formed via the interlayer insulator
2
.
The upper conductive layer
12
and the lower conductive layer
11
are electrically connected to each other via a buried conductive layer
4
formed by filling a connection hole
2
c
, what is called a via hole, formed in the interlayer insulator
2
with tungsten (W) or the like on the connecting part between the lower conductive layer
11
and the upper conductive layer
12
.
In such a semiconductor device, for example, when the distance (d) between the patterns in the lower conductive layer
11
is shortened with the miniaturization of the device, the parasitic capacity between the patterns becomes a problem. In order to reduce the parasitic capacity, it is required to use a material of a dielectric constant as low as possible as the material of the interlayer insulator
2
interposed between the patterns.
It has been proposed that an SiOF film fabricated by using a material obtained by adding C
2
F
6
or NF
3
as a fluorine element to TEOS (tetraethyl orthosilicate) is used as the insulating film of a low dielectric constant (25th SSDM' 93, p. 161 and 40th United Lecture Conference related to Applied Physics, Preprint, 1a-ZV-9).
In this case, however, it has been reported that the film quality deteriorates as the content of fluorine to be added increases and, accordingly, moisture resistance largely deteriorates.
On the other hand, formation of an SiOF film by using an SiF
4
/O
2
gas in which fluorine is contained in a raw material gas structure has been being examined for stabilization of the film quality (40th United Lecture Conference related to Applied Physics, Preprint, 31p-ZV-1).
The dielectric constant of the SiOF film obtained by the method is, however, at most about 3.8 due to moisture absorbency.
On the other hand, aiming at the dielectric constant of 3.8 or lower, it has been proposed to use an organic resin material as the material of the interlayer insulator.
For example, a method of fabricating an insulating film made of an organic resin material having a low dielectric constant by using both of a thermal decomposing reaction and a thermal polymerizing reaction of a raw material gas of a dimmer has been proposed. The dielectric constant of an organic resin layer formed by the method is as low as about 2.3 (VLSI/ULSI MULTI LEVEL INTERCONNECTION CONFERENCE, p. 207, 1996).
Another example relates to polyaryl ether as a material used in a rotational application method.
In the case of fabricating a semiconductor device of what is called a multilayer wiring structure in which at least two conductive layers such as wiring layers are stacked via the interlayer insulator as described above, an operation of opening a connection hole in the interlayer insulator is performed in order to connect the upper and lower wiring layers (that is, the upper and lower conductive layers) disposed so as to sandwich the interlayer insulator.
The operation of opening the connection hole is generally carried out by etching using a photoresist layer as an etching mask. In the case of using the organic resin insulating film of a low dielectric constant as the interlayer insulator, the etch selectivity between the organic resin insulating film of a low dielectric constant and the photoresist layer made of a photosensitive resin is low. Consequently, the photoresist layer itself cannot be used as an etching mask.
When the organic resin insulating film of a low dielectric constant is used as the interlayer insulator, an opening such as the connection hole is etched in the insulating film by a method of forming a so-called hard mask layer serving as the etching mask on the organic resin insulating film of a low dielectric constant.
An example will be described by referring to
FIGS. 10A
to
10
C. In
FIGS. 10A
to
10
C, the same components as those in
FIG. 9
are designated by the same reference numerals and the description is omitted here.
First, as shown in
FIG. 10A
, a hard mask layer
5
made of SiO
2
or the like is deposited on the interlayer insulator
2
which is the organic resin insulating film of a low dielectric constant formed on the lower conductive layer
11
. The hard mask layer
5
is subjected to pattern etching. For this purpose, a photoresist layer
6
is applied on the hard mask layer
5
, a predetermined pattern is exposed and developed by photolithography on the photoresist layer
6
, and an opening
6
W is formed over a part where a connection hole
2
c
is to be formed in the interlayer insulator
2
.
As shown in
FIG. 10B
, by using the photoresist layer
6
as the etching mask, the hard mask layer
5
exposed through the opening
6
W is etched to form an opening
5
W below the opening
6
W.
After that, as shown in
FIG. 10C
, the interlayer insulator
2
exposed to the outside through the openings
6
W and
5
W is etched to thereby open the connection hole
2
c
as an object.
Although the etch selectivity between the photoresist layer
6
and the interlayer insulator
2
realized by the organic resin insulating film of a low dielectric constant is low, since SiO
2
having a high etch selectivity with the organic resin insulating film of a low dielectric constant is deposited on the interlayer insulator
2
, the connection hole
2
c
can be opened in the interlayer insulator
2
.
The connection hole
2
c
formed as mentioned above is filled with tungsten W or the like, thereby forming a buried conductive layer
4
as described in FIG.
9
.
In the case of using the organic resin insulating film of a low dielectric constant as the interlayer insulator, however, a problem such that the characteristic deteriorates and the reliability accordingly deteriorates occurs.
Specifically, as described above, the SiO
2
film used as a hard mask is deposited by CVD (Chemical Vapor Deposition) for opening the connection hole. In the formation of t

Affiliated with

Also associated with

Rating

Semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3132235