Multiplex communications – Wide area network – Packet switching
Patent
1992-12-10
1994-01-04
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
3701053, 370 84, 375118, 375111, H04J 306
Patent
active
052766888
ABSTRACT:
A circuit arrangement for adjusting the bit rates of two signals of which the higher bit rate signal is structured in frames, includes a buffer memory (2), a write counter and a read counter (6, 8) as well as a phase comparator (7) and a control circuit (10). With these modules the bits of the lower bit rate signal are arranged in the frames of the higher bit rate signal. In addition to these bits negative or positive stuff bits are also inserted in the frames. In order to avoid jitter when the lower bit rate signal is recovered at the receiver end, the phase different between the two signals is determined more accurately. This effected with a counter (55, 56) whose count is applied to the phase comparator (7) to determine the digits after the decimal point for the phase difference. Furthermore, a controller (9) is provided in an automatic control system (7, 10, 8) for controlling the clock for the read counter (8), to which controller the output signal of the phase comparator (7), as well as information about the number of positive or negative bits to be stuffed during the next stuffing operation, is applied.
REFERENCES:
patent: 4224473 (1980-09-01), Kaul et al.
patent: 4791652 (1988-12-01), McEachern et al.
patent: 4811340 (1989-03-01), McEachern et al.
patent: 5067126 (1991-11-01), Moore
"Measured Pluse Stuffing Jitter in Asynchronour DS-1/Sonet Multiplexing with and Without . . . " Grover et al., Elec. Let. (1987) vol. 23, pp. 959-961.
Biren Steven R.
Jung Min
Olms Douglas W.
U.S. Philips Corporation
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