Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2000-09-28
2003-02-11
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C438S692000
Reexamination Certificate
active
06518074
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates to failure analysis of integrated circuit (IC) devices, and in particular, to an etch process for backside analysis.
2. Description of Related Art
The complexity of integrated circuits continues to increase as their dimensions decrease. The increased complexity drives up production costs, mandating efforts to limit the number of defective products. Despite the advance of technology, the wafer production process still has yields significantly less than 100%, making failure analysis an important tool for semiconductor manufacturers to limit the amount of defective product.
Numerous problems cause ICs to become defective. For example, minute dust particles can cause short circuits or open circuits, oxide can breakdown or be too thin, and metal can over-concentrate or under-concentrate in specific locations. A failure analysis typically starts by locating the site of the failure, a technique known as failure site isolation. This can be done electrically by using electrical test results to identify the failure location. Alternatively, physical methods can be employed to detect secondary effects of the failure such as identifying light emission or infra-red emission from the failure site. Another physical method employs probing techniques to access nodes or nets within the IC.
The aforementioned complexity of ICs has reduced the effectiveness of purely electrical methods, particularly for logic and analog circuits. Probing techniques also suffer from this complexity, e.g, from ICs having multiple layers of metallization making nodes inaccessible. In addition, modern packaging techniques-such as flip chip-make probing techniques problematic. Hence, backside physical analysis techniques have been developed, avoiding the top or active side of the die and the problems associated with purely electrical or probing techniques. For example, both infra-red and visible light emission (optical de-bug ) analyses as well as focused ion beam, optical beam induced current, and laser voltage probing techniques can be accomplished from the backside of the IC.
Regardless of the particular technique employed, a backside analysis will generally begin by using a milling machine to remove a backside portion of the IC, exposing the silicon substrate of the die used to form the IC. This silicon substrate is normally around 700 microns thick and must be thinned and then polished to permit light emissions to pass through what remains of the substrate. Silicon, however, is very hard and quite brittle, which complicates the back-thinning of the chip. Microscopic cracks introduced by the milling have a tendency to propagate. In addition, milling through the metal die paddle or through a metal heat shield tends to drive bits of metal into the silicon, which also causes cracking. These propagated cracks, affect the backside analysis, giving false or misleading results. As a result, the milling must be done very carefully, introducing substantial delay in a backside analysis. Milling through the epoxy packaging material introduces further delay because the epoxy is extremely tenacious and tends to foul the milling head.
Mechanical milling may be accomplished in one tool but generally requires multiple machine set-ups to accomplish a series of grinds. Initially, a rough grind through the epoxy packaging material and metallic heat shield (if applicable) uses a coarse grit having a 60 micron (&mgr;M) dimension. Because a silicon die is generally bonded directly to the metallic heat shield, as the milling head grinds through the heat shield, the coarse grit will often drive microscopic bits of metal into the die, generating cracks. As the milling bit grinds through the die, the grit dimension is reduced, until finally a 3 &mgr;M grit is used for the polishing stage. The multiple stages of grinding the die often introduces inclusions and cracks into the die, producing artifacts and false results in the ensuing backside optical analysis.
Accordingly, there is a need in the art for backside thinning processes which avoid the problems introduced by mechanical back-thinning of silicon substrates and milling of associated metallic packaging structures and packaging.
SUMMARY
In accordance with one aspect of the invention, a dry etch process substantially back-thins a die through an exposed backside surface. A wet etch process exposes the backside surface of the die. After the die has been dry etched, a conventional polishing step prepares the die for a backside debug analysis.
The invention will be more fully understood upon consideration of the detailed description below, taken together with the accompanying drawings.
REFERENCES:
patent: 4284072 (1981-08-01), McKaveney
patent: 4980019 (1990-12-01), Baerg
patent: 5980720 (1999-11-01), Park et al.
patent: 6077452 (2000-06-01), Litvak
patent: 6080675 (2000-06-01), Prall et al.
patent: 6087199 (2000-07-01), Pogge et al.
patent: 6156580 (2000-12-01), Wooten et al.
patent: 6168960 (2001-01-01), Ii
patent: 6261870 (2001-07-01), Haehn et al.
patent: 6395580 (2002-05-01), Tseng
patent: 6403439 (2002-06-01), Lee
patent: 6428718 (2002-08-01), Birdsley et al.
Zant, Peter Van, “Microchip Fabrication, a Practical Guide to Semiconductor Manufacturing”, Apr. 3, 2000, McGraw hill, 4th Ed., pp. 63-65, 262, 270, 567-568, and 612.*
Zant, Peter Van, “Microchip Fabrication, A practical Guide to Semiconductor Manufacturing”, 4thEd., pp. 257-271.
Acedo Henry
Johnson Smith J.
Nguyen Hiep V.
Weaver Kevin
National Semiconductor Corporation
Niebling John F.
Skjerven Morrill LLP
Whitmore Stacy A
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