Television – Stereoscopic – Stereoscopic display device
Reexamination Certificate
1999-05-03
2003-06-03
Philippe, Gims S. (Department: 2613)
Television
Stereoscopic
Stereoscopic display device
C345S089000, C345S690000
Reexamination Certificate
active
06573928
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a display controller and to a three dimensional (3D) display including such a controller. The present invention also relates to a method of reducing crosstalk, for instance between different views in a 3D display.
DESCRIPTION OF THE RELATED ART
FIG. 1
of the accompanying drawings illustrates the layout of picture elements (pixels) of a standard type of liquid crystal device (LCD). The LCD is for use in a colour display and comprises red, green and blue pixels indicated by R, G and B. The pixels are arranged as columns Col
0
to Col
5
with the red, green and blue pixels being aligned vertically. Thus, the left-most column of pixels Col
0
displays the left-most strip of an image to be displayed, the adjacent column Col
1
to the right displays the next column of the image and so on.
As illustrated in
FIG. 2
a
of the accompanying drawings, such an LCD may be used to form a 3D autostereoscopic display. The 3D display comprises an LCD
1
which acts as a spatial light modulator (SLM) for modulating light from a backlight
2
. A parallax optic cooperates with the LCD
1
in order to form viewing windows.
FIG. 2
a
illustrates a 3D autostereoscopic display of the front parallax barrier type in which the parallax optic comprises a parallax barrier
3
. The parallax barrier
3
comprises a plurality of parallel vertically extending laterally evenly spaced slits such as
4
, each of which is aligned with the middle of a pair of individual colour pixel columns. For instance, the slit indicated at
4
in
FIG. 2
a
is aligned with a column
5
of blue pixels and a column
6
of green pixels.
FIG. 2
b
illustrates the viewing window structure for a two view autostereoscopic 3D display of the type shown in
FIG. 2
a
. By spatially multiplexing two views forming a stereoscopic pair across the LCD
1
, the left and right views are visible in viewing windows
7
such that, provided an observer is disposed such that the left eye is in a left viewing window L and the right eye is in a right viewing window R, a 3D image can be perceived. Such positions are referred to as orthoscopic positions and are illustrated at
8
,
9
and
10
in
FIG. 2
b.
FIG. 2
b
also illustrates pseudoscopic viewing positions
11
to
14
. When the observer is in one of these positions, the left eye views the right eye image whereas the right eye views the left eye image. Such viewing positions should be avoided.
In order to ensure that the left and right viewing windows occur in the correct locations, left and right image data are supplied to an LCD of the type shown in
FIG. 1
in the way illustrated in FIG.
3
. The colour image data for the left-most strip of the left image are displayed by the red, green and blue pixels columns indicated at Col
0
Left. Similarly, the colour data for the left-most strip of the right eye view are displayed by the columns of pixels indicated at Col
0
Right. This arrangement ensures that the image data for the left and right views are sent to the appropriate left and right viewing windows. This arrangement also ensures that all three pixel colours R, G and B are used to display each view strip. Thus, as compared with the layout shown out in
FIG. 1
, the red and blue pixels of the left-most column display image data of the left view whereas the green pixels of the left-most column display image data of the right view. In the next column, the red and blue pixels display image data of the right view whereas the green pixels display image data of the left view. Thus, when using a standard LCD
1
of the type illustrated in
FIGS. 1
to
3
, interlacing of left and right view image data with “swapping” of the green components between columns of RGB pixels is necessary. Of course, depending upon the display set-up, the red or blue components rather than the green components may be swapped.
A standard PC (computer) is not capable of performing such interlacing and green (or red or blue) component swapping at standard video frame rate because every pixel “write” operation has to be modified compared with displaying a two dimensional (2D) image in the standard layout illustrated in FIG.
1
.
Autostereoscopic 3D displays using flat panel LCDs are disclosed in British patent application numbers 9619097.0 and 9702259.4, European patent publication numbers 724175, 696144,645926, 389842, and U.S. Pat. Nos. 5,553,203 and 5,264,946.
FIG. 4
a
of the accompanying drawings illustrates part of a known type of video board for use in computers. Examples of such video boards are disclosed in ARM VIDC
20
Datasheet, Advanced Risc Machines Limited, February 1995, Fuchs et al, “Pixel planes: a VLSI-oriented design for a raster graphic engine”, VLSI Design, third quarter 1981, pp 20-28, and Harrel et al, “Graphic rendering architecture for a high performance desktop work station”, Proceedings of ACM Siggraph conference, 1993, pp 93-100. The general layout of such an arrangement is illustrated in
FIG. 4
a
of the accompanying drawings. Data to be displayed are supplied in serial form on a data bus
20
and addresses defining screen locations for the pixels are supplied on an address bus
21
. The data bus
20
is connected to the inputs of several banks of random access memories (two shown in the drawing) such as VRAMs
22
and
23
. The address bus
21
is connected to a memory management system
24
which converts the screen addresses into memory addresses which are supplied to the address inputs of the memories
22
and
23
.
Output ports of the memories
22
and
23
are connected via a latch circuit
30
to a first in first out (FIFO) register
25
of a video controller
26
, which additionally comprises circuit
27
for supplying red (R), green (G), blue (B), horizontal synchronisation (H) and vertical synchronisation (V) signals to a display device. The memories
22
and
23
and the register
25
are controlled so that individual pixel data are read alternately from the memories
22
and
23
and supplied in the correct order to the circuit
27
. The circuit
27
, for instance, serialises the data and contains a colour pallet look up table (LUT) and digital-analogue converters (DAC). Timing signals for the video board are generated by a timing generator
28
.
FIG. 4
b
illustrates the latch circuit
30
in more detail. The latch circuit
30
comprises latches
40
and
41
connected to the output ports of the memories
22
and
23
, respectively. Each of the latches
40
and
41
comprises
32
one bit latches arranged as groups of eight for latching R, G, B and A data from the respective memory. The eight bits A are described hereinafter. The latches
40
and
41
have latch enable inputs connected together and to an output of the timing generator
28
supplying latch enable signals L.
The latch circuit
30
further comprises three switching circuits
42
,
43
and
44
, each of which comprises eight individual switching elements whose control inputs are connected together. The control inputs of the switching circuits
42
,
43
and
44
are connected together and to an output of the timing generator
28
supplying a switching signal SW. The timing generator
28
has a further output supplying write enable signals F to the register
25
.
FIG. 4
c
is a timing diagram illustrating the signals L, SW and F. These signals are synchronised by the timing generator
28
to the rest of the video board.
When new display data are available at the output ports of the memories
22
and
23
, the latch enable signal L goes high, for instance as illustrated at time t
1
. The latches
40
and
41
thus latch the display data. Shortly after the latch enable signal L has returned to zero, the switching signal SW rises to a high level. At time t
2
the switching circuits
42
,
43
and
44
are switched to the state illustrated in
FIG. 4
b
such that the RGB outputs of the latch
40
are connected to the register
25
. At time t
3
a write enable signal f is supplied to the register
25
so that the RGB data from the latch
40
are writ
Holliman Nicolas Steven
Jones Graham Roger
Philippe Gims S.
Renner Otto Boisselle & Sklar
Sharp Kabushiki Kaisha
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