Smear compensation circuit for a solid state imager

Details Smear compensation circuit for a solid state imager Smear compensation circuit for a solid state imager

1994-05-31

1996-01-16

Mancuso, Joseph

Television

Camera, system and detail

Combined image signal generator and general image signal...

348249, H04N 5335

Patent

active

054852056

ABSTRACT:
The present invention is to provide a smear compensation circuit in which the memory capacity of a memory can be reduced without deteriorating the quality of a reproduced image based on an output of a solid state image pickup device.
A peak value of the video signal in the vertical blanking period is detected by a peak detecting circuit (10) and a gain of smear data written in a 1H memory (8) is adjusted by (xA) in response to the detected peak value, whereby the smear data is stored in the memory having a restricted memory capacity. Further, when the data is read out from the 1H memory (8), the gain of the read-out data is adjusted in an opposite manner (x1/A) to thereby obtain a smear component of the original level. Then, this smear component is subtracted from the video signal.

REFERENCES:
patent: 4010319 (1977-03-01), Levine
patent: 4516172 (1985-05-01), Miyata et al.
patent: 4547807 (1985-10-01), Mitani et al.
patent: 4558366 (1985-12-01), Nagumo
patent: 4581651 (1986-04-01), Miyata et al.
patent: 4608608 (1986-08-01), Nishizawa et al.
patent: 4742396 (1988-05-01), Bell
patent: 4851904 (1989-07-01), Miyazaki et al.
patent: 4875098 (1989-10-01), Shimizu et al.
patent: 4992873 (1991-02-01), Koslov et al.
patent: 5005082 (1991-04-01), Zdepski et al.
patent: 5016107 (1991-05-01), Sasson et al.
patent: 5046179 (1991-09-01), Uomori
patent: 5089894 (1992-02-01), Higashitsutsumi
patent: 5321522 (1994-06-01), Eschbach
Japanese Patent Abstracts of Japan, vol. 8, No. 3, Mar. 9, 1984, JP-A-58204679.
Japanese Patent Abstracts of Japan, vol. 9, No. 81, 10 Apr. 1985, JP-A-59 211 385.
JP 58-204679(A), Nov. 29, 1983, Sakuraba.
JP 58-219873(A), Dec. 21, 1983, Kobayashi.
JP 60-4378(A), Jan. 10, 1985, Suga.
JP 60-217764(A), Oct. 31, 1985, Watanabe.

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