Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2002-10-22
2003-12-02
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S537000, C345S084000, C345S100000
Reexamination Certificate
active
06657478
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Intention
The present invention relates to a voltage generation circuit employing a capacitor and a display unit comprising this voltage generation circuit.
2. Description of the Related Art
FIG. 41
illustrates an exemplary conventional voltage generation circuit employing a capacitor. The voltage generation circuit shown in
FIG. 41
comprises a capacitor (pumping capacitor) cp
1
, first and second p-channel MOS (metal oxide semiconductor) transistors pt
1
and pt
2
, an inverter circuit inv
1
and the like.
The first p-channel MOS transistor (driving transistor) pt
1
has a drain terminal D and a gate terminal G connected to a node nd
1
and a source terminal S defining a voltage output terminal
30
outputting a negative voltage VBB. The second p-channel transistor pt
2
has a source terminal S connected to the node nd
1
, a gate terminal G connected to the inverter circuit inv
1
, and a drain terminal D defining a ground terminal.
The capacitor cp
1
is formed by a p-channel transistor having a source terminal and a drain terminal connected in common with each other and a gate terminal G connected to the node nd
1
. A clock signal CLK is input in the capacitor cp
1
and the inverter circuit inv
1
through an input terminal
10
.
The outline of operation of the voltage generation circuit having the aforementioned structure for generating the voltage (negative voltage) VBB is now described.
When the clock signal CLK goes low in logic (hereinafter simply referred to as “low”), the potential Vn
1
of the node nd
1
lowers to reach a negative voltage. When the potential Vn
1
of the node nd
1
lowers below the potential VBB of the source terminal S of the first p-channel MOS transistor pt
1
in excess of the threshold voltage Vthp
1
of the first p-channel MOS transistor pt
1
, the first p-channel transistor pt
1
is turned on.
At this time, charges proportional to the capacitance of the capacitor cp
1
flow from the source terminal S of the first p-channel MOS transistor pt
1
toward the node nd
1
. These charges are stored in the capacitor cp
1
since the second p-channel MOS transistor pt
2
is in an OFF state, and the potential Vn
1
of the node nd
1
rises in response to these charges.
When the clock signal CLK goes high in logic (hereinafter simply referred to as “high”), the potential Vn
1
of the node nd
1
is pulled up by a level corresponding to the high level (VDD) of the clock signal CLK, to further rise.
When the clock signal CLK goes high, further, a low-level signal is input in the second p-channel MOS transistor pt
2
through the inverter circuit inv
1
, to turn on the second p-channel MOS transistor pt
2
. At this time, the charges stored in the capacitor cp
1
are extracted to the ground terminal (GND), and the potential Vn
1
of the node nd
1
lowers.
Thus, the charges are pumped from the source terminal S of the first p-channel MOS transistor pt
1
to the ground terminal (GND) every cycle of the clock signal CLK, thereby rendering the voltage of the source terminal S of the first p-channel MOS transistor pt
1
negative.
FIG. 42
shows a voltage generation circuit known as an example improving the pumping efficiency of the aforementioned conventional voltage generation circuit. This voltage generation circuit uses two conventional voltage generation circuits described above, and applies clock signals CLK and /CLK inverted in phase to each other to terminals of pumping capacitors cp
1
and cp
2
respectively thereby improving the pumping efficiency thereof and reducing the time for attaining a prescribed negative voltage.
While the aforementioned conventional voltage generation circuit effectively generates the voltage (negative voltage) VBB with a simple structure, the theoretical value of the achieved negative voltage (VBB) is (−VDD+Vthp
1
+Vthp
2
) in FIG.
41
and (−VDD+Vthp
1
) in
FIG. 42
, which is less than the maximum logical value (−VDD) by the threshold voltage (Vthp
1
, Vthp
2
) of the first and second p-channel MOS transistors pt
1
and pt
2
.
As the output negative voltage VBB lowers, further, the potential difference between the source terminal S of the first p-channel MOS transistor pt
1
and the node nd
1
, i.e., the gate-to-source voltage of the first p-channel MOS transistor pt
1
reduces to lower the drivability of the first p-channel MOS transistor pt
1
.
In recent years, a voltage generation circuit having high current drivability is required in view of current drivability necessary for controlling word lines of a DRAM (dynamic random access memory) with a negative bias or in view of reduction in power consumption and attainment of operating margins of pixel transistors in a liquid crystal display unit or the like. However, the aforementioned conventional voltage generation circuit cannot sufficiently satisfy such requirements due to the low current drivability.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a voltage generation circuit capable of obtaining a high voltage with high current drivability and a display unit comprising this voltage generator.
A voltage generation circuit according to an aspect of the present invention has a capacitor and generates a prescribed voltage through a node connected to a first terminal of the capacitor, and further comprises an n-channel transistor having one of a source terminal and a drain terminal connected to the node with the other one of the source terminal and the drain terminal defining an output terminal outputting the prescribed voltage and a p-channel transistor having one of a source terminal and a drain terminal connected to the node with the other one of the source terminal and the drain terminal defining a reference potential terminal, while gate terminals of the n-channel transistor and the p-channel transistor are connected in common, one of two clock signals inverted in phase to each other is applied to a second terminal of the capacitor, and the other one of the two clock signals is applied to the gate terminals connected in common.
The voltage generation circuit can obtain an output voltage not influenced by the threshold voltage Vth of the n-channel transistor serving as a driving transistor. When generating a negative voltage, for example, the driving transistor is reliably turned on also when the output negative voltage lowers, whereby the drivability of the driving transistor can be sufficiently secured regardless of the value of the negative voltage. Further, the n-channel transistor is employed as the driving transistor, whereby the operating speed of the voltage generation circuit can be increased as compared with the case of employing the p-channel transistor, and the drivability can be increased. When securing ability equivalent to that of the p-channel transistor with the n-channel transistor, further, the element areas of the transistors can be reduced.
The voltage generation circuit is preferably formed on a P-type semiconductor substrate having a triple well structure, the n-channel transistor preferably includes a MOSFET formed on a P-type well to which the output terminal is connected for obtaining its back gate potential, the p-channel transistor preferably includes a MOSFET formed on an N-type well to which a positive potential is applied for obtaining its back gate potential, and the capacitor preferably includes an n-channel transistor separately formed on a P-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the node.
The voltage generation circuit may be formed on an N-type semiconductor substrate having a double well structure, the n-channel transistor may include a MOSFET formed on a P-type well to which the output terminal is connected for obtaining its back gate potential, the p-channel transistor may include a MOSFET formed on an N-type well to which a positive potential is applied for obtaining its back gate potential, and the capacitor may include an n-channel transistor separately formed on a
Armstrong Westerman & Hattori, LLP
Cunningham Terry D.
Sanyo Electric Co,. Ltd.
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