RF power transistor having low parasitic impedance input...

Details RF power transistor having low parasitic impedance input... RF power transistor having low parasitic impedance input...

2000-09-28

2003-02-18

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Bipolar transistor structure

Plural non-isolated transistor structures in same structure

C438S205000, C438S313000, C438S340000

Reexamination Certificate

active

06521972

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates generally to RF power transistors, and more particularly the invention relates to providing a low parasitic impedance input/output feed structure in a distributed power transistor.
Power transistors (MESFET, MOSFET, BIPOLAR, HBT) for RF and Microwave frequencies are made of multiple building blocks or individual transistors which are driven in parallel with the outputs of the transistors combined as the power output. A commonly used drive structure is the “divide-by-two” feed, which is used over and again as shown in FIG.
1
. In
FIG. 1
, the input signal is applied at terminal
10
with the feed path
12
divided by 2 as many times as necessary to drive the individual transistors
14
. The “divide-by-two” pattern can be used several times as long as each path has equal input length to the individual transistors. The input terminals of transistors
14
can be interconnected also by line
15
. The output side is “power combined” by the same structure in reverse order.
The high frequency response of a transistor is affected strongly by the input capacitance to the transistor, which is the gate to source capacitance in a field effect transistor and a base-to-emitter capacitance in BIPOLAR and HBT transistors. Therefore, the standard rule of thumb has been to avoid the overlap of the feed structure to any source or emitter electrode connection and thereby minimize the input capacitance.
The feed structure represents a large inductance in a high power transistor with the input inductance adversely effecting the input matching circuit bandwidth. Also, an “odd mode” oscillation can occur with a large input and output impedance among the building block transistors as illustrated in FIG.
2
. As shown in
FIG. 2
, the input at contact
10
is applied through inductors
12
to the base of transistors
14
, the output is taken at the collectors and applied through inductors
18
to the output terminal
20
. As illustrated by the dotted signal configuration
22
, the inductive feed can cause an oscillation with the input signal at transistors
14
being 180° out of phase thereby canceling the signal of the transistors at input
10
and output
20
.
The present invention is directed to an improved low inductance power feed structure and in which possible “odd mode” operation is reduced.
SUMMARY OF THE INVENTION
In accordance with the invention, the input/output feed structure to the plurality of transistor elements in an RF power transistor is placed in close proximity to a ground plane whereby the feed structure functions as a low impedance microstrip line in feeding each of the transistor elements. The ground plane is connected through vias, for example, to a backside ground plane on the bottom of the transistor semiconductor chip.
More particularly, an RF power transistor includes a semiconductor body having a plurality of individual transistors therein, a first ground plane on a bottom surface of the semiconductor body and a second ground plane on a top surface of the semiconductor body which is electrically connected to the first ground plane and to which common elements of individual transistors are connected. A dielectric insulating layer is provided over the second ground plane, and a feed structure is then formed on the insulating layer and overlying the second ground plane, the feed structure preferably comprising a metal layer which has been selectively patterned to form the feedlines to the individual transistors.
The semiconductor body can comprise silicon or a III-IV semiconductor material such as gallium arsenide or indium phosphide. The insulating layer is preferably silicon oxide, silicon nitride, polyimide, or a combination thereof. The individual transistor elements can be a MESFET, MOSFET, BIPOLAR or HETROJUNCTION BIPOLAR transistor (HBT).
Not only is the parasitic impedance provided by the microstrip line reduced, but also total transistor size can be increased before the “odd mode oscillation” occurs.
The invention and objects and features thereof will be more readily apparent from the following detailed description and dependent claims when taken with the drawings.


REFERENCES:
patent: 3651434 (1972-03-01), McGeough et al.
patent: 5939789 (1999-08-01), Kawai et al.
patent: 6114716 (2000-09-01), Boles et al.
patent: 6246102 (2001-06-01), Sauerbrey et al.
patent: 6310362 (2001-10-01), Takemura
patent: 6310372 (2001-10-01), Katayama et al.
patent: 6351133 (2002-02-01), Jones et al.
patent: 2258563 (1993-02-01), None
patent: 58032450 (1983-02-01), None
Ben G. Streetman and Sanjay Banerjee, Solid State Electronic Devices 2000, Prentice Hall, Inc., Fifth Edition, pp. 18-19.

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