Boots – shoes – and leggings
Patent
1996-04-23
1999-02-23
Teska, Kevin J.
Boots, shoes, and leggings
364490, G06F 1750
Patent
active
058751173
ABSTRACT:
An initial placement of cells for an integrated circuit chip is decomposed into a hierarchial order of groups of cells. The groups are routed simultaneously using parallel processors, and the results are recomposed to provide a global routing that provides a detailed mapping of cell interconnect congestion in the placement. Areas of high congestion are identified, and a congestion reduction algorithm is applied using the parallel processors to alter the placement in these areas simultaneously. The overall fitness of the placement is then computed, and if it has not attained a predetermined value, the steps of identifying congested areas and applying the congestion reduction algorithm to these areas are repeated. The cumulative error created by altering the placement without repeating the global routing is estimated, and if it exceeds a predetermined value, the global routing is also repeated.
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Boyle Douglas B.
Jones Edwin R.
Koford James S.
Rostoker Michael D.
Scepanovic Ranko
LSI Logic Corporation
Phan Thai
Teska Kevin J.
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