Delay locked loop for generating complementary clock signals

Details Delay locked loop for generating complementary clock signals Delay locked loop for generating complementary clock signals

2002-06-24

2003-12-09

Tan, Vibol (Department: 2819)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000, C327S163000, C327S276000, C327S277000, C327S299000

Reexamination Certificate

active

06661265

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a delay locked loop having a delay unit with a controllable delay time and a feedback loop, for controlling the delay time, complementary delayed clock signals being able to be tapped off.
Delay locked loops are used in circuits that operate digitally in order to generate clock signals with a predetermined phase angle. By way of example, in synchronously operated integrated semiconductor memories, so-called synchronous dynamic random access memories (SDRAMs), a delay loop is used to generate a clock signal while taking account of internal signal propagation times, which clock signal provides data that are to be output synchronously with an input clock signal fed to the integrated circuit at a different location.
For this purpose, in the delay locked loop, a phase detector is used to compare the clock signal fed to the delay unit on the input side with the clock signal output by the delay unit on the output side, the feedback loop additionally contains a fixed delay time which represents the downstream signal propagation times. A loop filter, for example embodied in a manner based on a counter, controls the delay time of the delay unit. The control loop adjusts the delay time to such an extent that the phase difference at the phase detector is corrected as far as possible to zero. The delay unit contains a multiplicity of cascaded delay elements, to each-of which a switch that can be driven by the counter is connected in order to switch the output signal of the respective delay element through to the output of the delay unit. The number of delay elements that are activated between the input and output of the delay unit determines the instantaneous delay time.
Such delay locked loops can be configured to generate complementary clock signals on the output side. The complementary clock signals are either processed further separately from one another or combined again to form a single-phase clock signal. In this case, it is important that two corresponding edges of the delayed clock signal and the delayed inverted clock signal are not phase-shifted with respect to one another.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a delay locked loop for generating complementary clock signals that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which generates two complementary delayed clock signals even at high frequencies in a manner free from errors and phase-synchronously with respect to one another.
With the foregoing and other objects in view there is provided, in accordance with the invention, a delay locked loop for generating complementary clock signals. The delay locked loop contains a delay unit having a terminal for receiving a clock signal to be delayed, a first output terminal for a delayed clock signal, a second output-terminal for a delayed complementary clock signal, and a control terminal for receiving a control signal controlling a delay time. The delay unit includes a series circuit of delay elements. The delay elements each have a series circuit formed by a first inverter with an output and a second inverter with an output, the second inverter is connected downstream of the first inverter. First switching elements are provided and receive and can be switched by the control signal. Each of the first switching elements has an input connected to the output of the first inverter of one of the delay elements. The first switching elements have outputs connected to each other and form a first common node, and the first common node is coupled to one of the first and second output terminals. Second switching elements are provided and receive and can be switched by the control signal. Each of the second switching elements has an input connected to the output of the second inverter of one of the delay elements. The second switching elements have outputs connected to each other and form a second common node, and the second common node is coupled to another of the first and second output terminals. A feedback loop feeds one of the delayed clock signal and the delayed complementary clock signal provided from the first output terminal and the second output terminal, respectfully, back to the control terminal.
In the case of the delay locked loop according to the invention, the delay unit contains delay elements that, for their part, in turn have a first and a second inverter connected in series one after the other. Only a single series circuit is provided for delaying the clock signal. Pulses for the inverted delayed output clock signal are tapped off at the outputs of the respective first inverters via switching elements, and the delayed non-inverted clock pulses are tapped off at the outputs of the respective second inverters via corresponding switches. The delay time is controlled and set by a respective one of the switches being activated in order to tap off the clock signal in accordance with the desired delay time at a suitable location on the delay path. The delay time is thus determined by the number of delay elements acting on the clock signal to be delayed. The configuration has the advantage that the outputs of all the first and all the second inverters are always connected up to the same capacitive load, namely either a downstream-connected inverter of the delay unit or a switching element for tapping off the non-inverted or inverted delayed clock signal. This ensures that all the edges of the clock signal propagating through the delay unit are delayed by exactly the same delay time within each inverter of the delay elements of the delay unit. Therefore, the inverted and the non-inverted delayed clock signals are always tapped off synchronously with respect to one another, to be precise independently of whether the tapping-off is effected at the beginning of the delay unit after a short set delay time or at the end of the delay unit after a long set delay time. The synchronism of tapped-off delayed inverted and delayed non-inverted clock signals remains even at high frequencies of the clock signal. The circuit is therefore particularly suitable for subsequently combining non-inverted and inverted delayed clock signals again to form a single-phase clock signal.
By way of example, if the synchronism of the inverted and non-inverted delayed clock signals were not present and differed in the case of tapping-off at the beginning of the delay unit compared with tapping-off at the end of the delay unit, then it would have to be expected that pulses would be suppressed at high frequencies of the clock signal to be delayed, at the output. Such a disadvantage no longer exists in the case of the invention.
After it has been tapped off, the inverted delayed output signal is again subjected to a further delay that corresponds precisely to the delay time of one of the always identical inverters of the delay unit. As a result, the synchronously tapped-off edges of the inverted and non-inverted delayed clock signals are brought exactly into temporal correspondence and oriented to one another. The additional delay time is effected by a non-inverting further delay element.
An in each case an identically constructed driver, for example an inverter, is again expediently connected downstream of the common node to which the switches joining the delay unit and serving for tapping off the inverted clock signal are connected and the common node to which the switching elements for tapping off the non-inverted clock signal are connected. All the switches that serve for tapping off the inverted and non-inverted delayed clock signals are tri-state gates. Tristate gates can be switched into a transmissive state and into a high-impedance state by a control signal. In the transmissive switching state, they forward a signal fed in on the input side in an inverted form. In the high-impedance state, they are blocked. All the tri-state gates are controlled in the delay locked loop by a loop filter that is driven by the feedback loop of the delay locked loo

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