Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2002-01-23
2003-02-18
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S212000, C327S214000, C326S098000
Reexamination Certificate
active
06522184
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a static-type master-slave flip-flop circuit.
2. Description of the Prior Art
With the advancement of micromachining and related technologies, LSIs (large-scale integrated circuits) have come to offer increasingly high operation speeds and increasingly high degrees of integration. To make high-speed LSIs commercially viable, it is essential to minimize their power consumption. This is because the higher the speed at which an LSI operates, the higher its power consumption, and, to stabilize its operation, it becomes necessary to provide it with some heat dissipation means such as a ceramic package or heat radiating fins. Inconveniently, this requires extra cost.
Moreover, in those small-size and light-weight portable appliances that have been gaining popularity in recent years, reduction of power consumption is essential also from the viewpoint of the duration of the battery by which they are powered. In particular, with flip-flop circuits operating at high speeds, which are prone to extremely high power consumption, it is advisable to adopt circuit desigins that minimize power consumption.
Conventionally, static-type master-slave flip-flop circuits that employ CMOS FETs (complementary metal-oxide semiconductor field-effect transistors) are widely used for their high-speed operation and comparatively low power consumption.
FIG. 8
shows an example of such a conventional static-type master-slave flip-flop circuit. How this flip-flop circuit is configured and how it operates will be described below.
In
FIG. 8
, D represents a data input signal, CK represents a clock input signal, and Q represents a data output signal. The clock signal CK that has been fed to the flip-flop circuit is first inverted by the inverter circuit
200
to produce a signal CKX, which is then once again inverted by the inverter circuit
201
to produce a signal CK
1
. The signals CKX and CK
1
are applied to the transfer gates
202
,
205
,
206
, and
209
to turn them on/off in an appropriate manner.
FIG. 9
is a diagram illustrating the configuration of one of those transfer gates on the level of its constituent transistors. The transfer gate is composed of an N-channel MOS FET (hereafter referred to simply as an “NMOS transistor”)
210
and a P-channel MOS FET (hereafter referred to simply as a “PMOS transistor”)
211
connected in parallel. The NMOS and PMOS transistors
210
and
211
are turned on/off by receiving at their gates the signals CK and CKX respectively, which are inverted with respect to each other.
For example, when the signal CK is at a high level and the signal CKX is at a low level, the NMOS and PMOS transistors
210
and
211
are both turned on, connecting the two ends A and Y of the transfer gate to each other. On the other hand, when the signal CK is at a low level and the signal CKX is at a high level, the NMOS and PMOS transistors
210
and
211
are both turned off, disconnecting the two ends A and Y of the transfer gate from each other.
In the circuit shown in
FIG. 8
, when the clock input signal CK is at a low level, the inverter circuits
200
and
201
turn the signal CKX to a high level and turn the signal CK
1
to a low level. This turns the transfer gate
202
on, and thus the master latch delivers the data input signal D to the node
220
. When the data input signal D is at a low level, the inverter circuit
203
turns the level at the node
221
to a high level, and the inverter circuit
204
turns the level at the node
222
to a low level. At this time, the transfer gates
205
and
206
remain off, and thus the data delivered to the master latch is not transferred to the slave latch.
Next, when the clock signal CK turns to a high level, the inverter circuits
200
and
201
turn the signal CKX to a low level and turn the signal CK
1
to a high level. This turns the transfer gate
202
off and turns the transfer gates
205
and
206
on. Thus, in the master latch, the data fed thereto is held by the inverter circuits
203
and
204
and the transfer gate
205
.
Moreover, the transfer gate
206
thus turned on causes the signal present at the node
221
to be delivered to the node
223
of the slave latch. Thus, the inverter circuit
207
turns the data .output signal Q to a low level, and the inverter circuit
208
turns the level at the node
224
to a high level. At this time, the transfer gate
209
remains off.
Next, when the clock signal CK turns to a low level, the transfer gate
206
is turned off, and the transfer gate
209
is turned on. Thus, in the slave latch, the data is held so that the data output signal Q will be kept at a low level.
In this way, when the clock signal CK is at a low level, the data input signal D is fed to the master latch, and, when the clock signal CK turns to a high level, the data is transferred to the slave latch, causing the data output signal Q to be output. Thereafter, when the clock signal CK turns back to a low level, the slave latch holds the data output signal Q. In a similar manner, when the data input signal D is at a high level, a high level is output as the data output signal Q.
However, in this conventional flip-flop circuit (FIG.
8
), every time the clock signal CK changes its level, and regardless of the level of the data input signal D. currents flow to charge/discharge the gate capacitors in the six PMOS and six NMOS transistors constituting the inverter circuits
200
and
201
and the transfer gates
202
,
205
,
206
, and
209
as well as the drain capacitors within the inverter circuits
200
and
201
.
Moreover, in the inverter circuits
200
and
201
, which are each composed of a PMOS transistor and an NMOS transistor connected in series, there appears, just when the clock input signal CK changes its level, a period in which the PMOS and NMOS transistors are both kept on simultaneously. During this period, a current (called a through current) flows from the supplied voltage directly to ground GND, increasing power consumption.
Furthermore, as shown in
FIG. 10
, a PMOS transistor is on when its gate voltage is in a range R
1
lower than a voltage VDD−VthP, which equals to its threshold voltage VthP subtracted from the supplied voltage VDD; on the other hand, an NMOS transistor is on when its gate voltage is in a range R
2
higher than its threshold voltage Vthn.
For example, in any of the above-mentioned inverter circuits, before the clock signal fed thereto starts rising, i.e. when it is at a low level, the PMOS transistor is on and the NMOS transistor is off. When the clock signal reaches the voltage Vthn, the NMOS transistor, which receives the clock signal at its gate, is turned on. When the clock signal reaches the voltage VDD−VthP, the PMOS transistor is turned off.
Thus, while the signal CKX is rising, there appears, starting when the signal CKX reaches the voltage Vthn and ending when it reaches the voltage VDD−VthP, a period in which the NMOS transistor of the transfer gate
202
and the PMOS transistor of the transfer gate
205
are both kept on simultaneously. Similarly, while the signal CK
1
is falling, there appears a period in which the PMOS transistor of the transfer gate
202
and the NMOS transistor of the transfer gate
205
are kept on simultaneously.
As a result, when the data that is to be received next happens to be contrary to the data already held in the master latch, a through current flows through the transfer gates
202
and
205
between the data input signal D and the output of the inverter circuit
204
. Similarly, also when data is fed from the master latch to the slave latch, if the output of the inverter circuit
203
is contrary to the output of the inverter circuit
208
, a through current flows through the transfer gates
206
and
209
.
Moreover, the signals CKX and CK
1
, which are produced by the inverter circuits
200
and
201
, have a phase difference, which prevents the transfer gates
202
and
205
from being turned on/off simultaneously at all times. T
Callahan Timothy P.
Nguyen Minh
Sharp Kabushiki Kaisha
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