Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-01-14
2003-11-04
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185030
Reexamination Certificate
active
06643179
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and a circuit for dynamic reading of a memory cell, in particular a multi-level nonvolatile memory cell.
2. Description of the Related Art
As is known, the need for nonvolatile memories having increasingly larger densities has led to manufacturing multi-level memories wherein the information, stored as charge quantity in a floating-gate region, is encoded by fractioning the entrapped charge. In this way, the characteristic of a multilevel flash cell is described by a number of curves representing the pattern of the drain current Ids as a function of the gate voltage Vgs, each curve being associated to a different logic value. For example,
FIG. 1
shows the characteristic of a four-level (2-bit) flash cell which stores the bits “
11
”, “
10
”, “
01
” and “00”, corresponding to threshold voltages Vt
1
, Vt
2
, Vt
3
and Vt
4
.
In fact, for a memory array comprising of a plurality of memory cells, the characteristics are no longer representable by a single straight line, but form distributions of different amplitude that are spaced apart by an amount sufficient to distinguish them from one another, as shown in 2 and 3, wherein
FIG. 2
illustrates the distribution of the threshold voltages for an array of flash cells with 2 bits per cell, and
FIG. 3
shows the corresponding distribution of characteristics.
Reading of multi-level cells is carried out evaluating the current or the voltage.
Current reading is based on comparing the current flowing in a cell at a preset gate voltage Vgs and the current flowing in a reference cell, the characteristic of which is intermediate between the distributions of the programmed cells, as shown in FIG.
3
. The comparison is made after a current-to-voltage conversion, both of the current of the cell and of the reference current. Current reading requires the cell to absorb current, and hence the reading voltage Vr applied to the control gate terminal of the cell must at least be higher than the last but one threshold voltage (in the case of four levels, higher than Vt
3
).
Current reading has a number of problems, the main ones due to:
source resistance of the cell which, for cells belonging to the distribution “11” and because of the high current absorption, causes an undesired voltage drop, and thus to a cell gain variation;
drain-contact resistance, which causes an effect similar to the above;
resistance of the metal connections, which, in new fabrication processes, assumes an ever increasing importance; and
resistance caused by the pass transistors of the column decoder.
As a whole, the result is a reduction in current dynamics. Consequently, the comparator that compares the voltages after current-to-voltage conversion must have a greater sensitivity. In addition, the actual characteristics differ with respect to the ideal ones, as shown in FIG.
4
. In practice, the difference between the actual plot and the ideal plot in the array cells is all the greater, the higher the current absorbed by the cell. The characteristics of the reference cells are not modified in the same way, in that these cells may be designed so as to minimize the parasitic effects referred to above.
For example, consider a cell with a gain of 20 &mgr;A/V. If the cell is erased at 0.5 V, it absorbs a current of 110 &mgr;A at a gate voltage Vr=6 V, whereas if it has a threshold voltage of 5.5 V, it absorbs 10 &mgr;A.
In these conditions, the ideal current dynamics is 100 &mgr;A, and the distance between each reference current and the current of the nearest cell is 10 &mgr;A, whereas their distance, as regards the threshold voltage, is 0.5 V. The actual dynamics is instead reduced owing to the parasitic effects, which are typically approximately 20 &mgr;A. In order to compensate such effects, the distances of the reference curves from the cell curves are in general optimized so as to have minimum distances of 6-8 &mgr;A. However, this limits the number of levels storable in a single cell, owing to the difficulty in distinguishing characteristics that are very close to one another.
Suppose, in fact, that four bits are to be stored in a single memory cell. The voltage range including the characteristics remains the same as in the two-bit case (between 0.5 V and 6.5 V), for problems of reliability and operation, with a reading voltage Vr=6 V.
For simplicity, suppose a dynamics of 100 &mgr;A and sixteen equally spaced distributions. In these conditions, the sum of the width of a distribution and the distance from the next distribution is smaller than 7 &mgr;A. Setting the amplitude of each distribution equal to the distance between the distributions, each distribution is 3.5 &mgr;A wide and is at a distance of 3.5 &mgr;A from the adjacent distributions; the reference characteristic set between two distributions is at a distance of 1.75 &mgr;A from each of them. In real conditions, the sensitivity of the comparator must be approximately 1 &mgr;A.
In conclusion, reading of multi-level cells with more than two bits per cell becomes complex.
To overcome the above problems, U.S. Pat. No. 6,034,888, assigned to STMicroelectronics Srl, proposes a voltage reading method using a closed-loop circuit (see FIG.
5
). In this circuit, the current of the cell to be read is compared with a reference current, and the gate voltage of the cell is modulated until reaching the equilibrium of the system. Thereby, the gate voltage of the cell reaches a value that can be defined as the threshold value of the cell.
However, also this solution is not free from problems, due to the need for an A/D converter able to read the voltage on the gate terminal of the cell, and to the constraint of not being able to read more than one cell at a time, since the row is in common to more than one cell and cannot assume different voltage values.
The solutions devised for solving the above problems moreover involve other disadvantages (increase in read time, greater area) and in any case call for the capacity to discriminate very small currents. On the other hand, the new technologies, involving a reduction in the cell dimensions, lead in turn to a reduction in the cell current, even though solutions are known for reducing the parasitic effects that determine the losses of linearity.
In practice, the new cells operate at ever smaller currents, even though the characteristics could be maintained parallel.
BRIEF SUMMARY OF THE INVENTION
An embodiment of the present invention provides a method and a circuit for reading multi-level memory cells, which operate properly even in the presence of low cell currents.
In practice, the invention is based on the integration in time of the electric charge supplied to a memory cell to be read through a charging step or discharging step of a capacitive element.
REFERENCES:
patent: 5748534 (1998-05-01), Dunlap et al.
patent: 5909393 (1999-06-01), Tran et al.
patent: 5999454 (1999-12-01), Smith
patent: 6034888 (2000-03-01), Pasotti et al.
patent: 6134147 (2000-10-01), Kaneda
patent: 6337808 (2002-01-01), Forbes
patent: 6480421 (2002-11-01), Osama et al.
patent: 0 833 340 (1998-04-01), None
Campardo Giovanni
Micheloni Rino
Iannucci Robert
Jorgenson Lisa K.
Nguyen Tan T.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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