Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2002-04-30
2003-08-05
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S240000
Reexamination Certificate
active
06602722
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a capacitor incorporated in a semiconductor device and, more particularly, to a process for forming a capacitor and an apparatus for forming the capacitor.
DESCRIPTION OF THE RELATED ART
A dynamic random access memory is a typical example of the semiconductor device, and the dynamic random access memory cell is implemented by a series combination of an access transistor and a storage capacitor. The circuit components of the dynamic random access memory device have been scaled down. Although the area assigned to each storage capacitor is reduced, a data bit to be stored requires the storage capacitor to have a large capacitance. Dielectric material with the perovskite structure has a large dielectric constant, and is attractive to the storage capacitor. Barium strontium titanate ((Ba, Sr)TiO
3
and strontium titanate SrTiO
3
are examples of the material with the perovskite structure.
Using the dielectric material with the perovskite structure, the prior art storage capacitor is fabricated as follows. First, a ruthenium layer is patterned into a lower capacitor electrode. The barium strontium titanate is deposited over the lower capacitor electrode by using a chemical vapor deposition at 400 degrees in centigrade. The barium strontium titanate is treated at 650 degrees in centigrade for 10 minutes, and is crystallized. The chemical vapor deposition and the crystallization are repeated several times. Finally, ruthenium is deposited over the barium strontium titanate layer, and the ruthenium layer is patterned into an upper capacitor electrode.
The prior art storage capacitor exhibits a large capacitance. However, the data holding characteristics are not acceptable. This is because of the fact that the leakage current flows across the barium strontium titanate layer. Moreover, the dielectric layer of barium strontium titanate is deteriorated, and the dielectric constant is lowered.
SUMMARY OF THE INVENTION
It is therefore an important object of the present invention to provide a capacitor which exhibits a large capacitance without serious leakage current and free from the deterioration of the dielectric layer.
The present inventors contemplated the problem, and found non-ignoreable amount of impurity in the barium strontium titanate. The impurity was carbon and hydrogen, which were considered to be produced through an elimination reaction at 300 degrees to 400 degrees in centigrade. The present inventors concluded that a low temperature heat treatment was required for the impurity.
The present inventors searched database for the low temperature heat treatment against the impurity. Two documents were found. One of the documents was disclosed by M. Kiyotoshi et al. in 1999 Symposium on VLSI Technology Digest of Technical Papers, p.p. 101-102. The paper taught a crystallization of barium strontium titanate through a heat treatment. However, the paper is silent to the low temperature heat treatment against the impurity.
The other document is Japanese Patent Publication of Unexamined Application No. 11-243177. The Japanese Patent Publication of Unexamined Application taught two-step formation of barium strontium titanate layer through a high temperature heat treatment. However, the Japanese Patent Publication of Unexamined Application was silent to the low temperature heat treatment against the impurity.
To accomplish the object, the present invention proposes to eliminate the impurity from the substance with the perovskite structure.
In accordance with one aspect of the present invention, there is provided a process for fabricating a capacitor comprising the steps of a) preparing a semiconductor structure having a semiconductor substrate, b) forming a first electrode on the semiconductor structure, c) depositing a complex oxide expressed as ABO
3
on the first electrode and d) completing a capacitor through a high temperature heat treatment for crystallizing the complex oxide; a low temperature heat treatment for eliminating impurities causative of degradation from the complex oxide and forming a second electrode on the complex oxide.
In accordance with another aspect of the present invention, there is provided an apparatus for fabricating a capacitor comprising a first chamber for depositing a complex oxide expressed as ABO
3
on a semiconductor structure having a first electrode, a second chamber for a high temperature heat treatment through which the complex oxide is crystallized, a third chamber for a low temperature heat treatment through which impurity causative of degradation is eliminated from the complex oxide and a transfer system for conveying the semiconductor structure from one of the first to third chambers to another without exposing the semiconductor structure to the atmosphere.
REFERENCES:
patent: 5434102 (1995-07-01), Watanabe et al.
patent: 5858851 (1999-01-01), Yamagata et al.
patent: 6010927 (2000-01-01), Jones, Jr. et al.
patent: 11-54721 (1999-02-01), None
patent: 11-177048 (1999-07-01), None
patent: 11-243177 (1999-09-01), None
patent: 11-297964 (1999-10-01), None
patent: 2000-332209 (2000-11-01), None
patent: 2000-349254 (2000-12-01), None
“In-situ Multi-Step (IMS) CVD Process of (Ba, Sr) TiO3using Hot Wall Batch Type reactor for DRAM Capacitor Dielectrics” by M. Kiyotoshi, et al., 1999 Symposium.
“Process for Fabricating Capacitor Having Dielectric Layer With Perovskite Structure and Apparatus for Fabricating the Same”, 1999.
Iizuka Toshihiro
Kato Yoshitake
Yamamoto Ichiro
Scully Scott Murphy & Presser
Tsai Jey
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