Polishing pad

Details Polishing pad Polishing pad

2002-03-25

2003-02-25

Hail, III, Joseph J. (Department: 3723)

Abrading

Flexible-member tool, per se

C451S006000, C451S008000, C451S009000, C451S041000, C451S063000, C451S287000, C451S283000

Reexamination Certificate

active

06524176

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The invention relates to a polishing pad, and more particularly, to a polishing pad with a plug having a height of the polishing pad.
2. Description of the Prior Art
When fabricating modern semiconductor integrated circuits (ICs), to prevent subsequent manufacturing processes from being adversely affected, the flatness of each deposition layer of an integrated circuit has to be considered. In fact, most high-density IC fabrication techniques make use of some method to form a planarized wafer surface at critical points in the manufacturing process. One method for achieving semiconductor wafer planarization or topography removal is the chemical mechanical polishing (CMP) process. The CMP process is a well-known technique for removing materials on a semiconductor wafer using a polishing device and polishing slurry. The combination of the mechanical movement of the polishing device relative to the wafer and the chemical reaction of the polishing slurry provides an effective abrasive force with chemical erosion to planarize the exposed surface of the wafer or a layer formed on the wafer.
Please refer to FIG.
1
.
FIG. 1
is a schematic diagram of a portion of a prior art CMP apparatus
10
. The CMP apparatus
10
includes a polishing platen
12
covered with a polishing pad
14
. The polishing pad
14
comprises a covering layer
16
and a backing layer
18
. The backing layer
18
serves as an interface between the covering layer
16
and the polishing platen
12
. The covering layer
16
is used in conjunction with polishing slurry
20
to polish a semiconductor wafer
22
placed on the polishing platen
12
. Furthermore, a window
24
is formed in the covering layer
16
and an aperture
26
is formed below the window
24
in the backing layer
18
. This window
24
is positioned such that it has a view of the semiconductor wafer
22
held by a polishing head during a portion of a platen's rotation. A laser interferometer
28
is fixed below the polishing platen
12
in a position enabling a laser beam to pass through the window
24
and then strike the surface of the overlying semiconductor wafer
22
during a time when the window
24
is adjacent the semiconductor wafer
22
. Thereafter, the CMP apparatus
10
analyzes the reflected laser beam from the semiconductor wafer
22
to determine the endpoint of the CMP process.
However, there may be residues of the polishing slurry, by-products of the CMP process, or condensed water droplets deposited on the bottom surface of the window
24
in the prior art CMP apparatus
10
. Thus, the laser beam traveling through the window
24
is scattered by the deposits. That is, either the laser beam emitted from the laser interferometer
28
or the laser beam reflected from the semiconductor wafer
22
is attenuated. Consequently, the endpoint detection of the CMP process is interfered with and the planarization of the semiconductor wafer
22
cannot be achieved.
SUMMARY OF INVENTION
It is therefore a primary objective of the claimed invention to provide a polishing pad to solve the above-mentioned problem.
According to the claimed invention, a polishing pad is disclosed. The polishing pad has a first layer, a second layer, a hole and a plug. The hole is formed in the polishing pad and has a first section in the first layer of the polishing pad and a second section in a second layer of the polishing pad. The plug is embedded in the hole and has an upper portion and a lower portion. The upper portion of the plug fits into the first section of the hole, and the lower portion of the plug fits into the second section of the hole.
It is an advantage of the claimed invention that the polishing pad has the plug with a height of the polishing pad so as to eliminate the interference of residues of polishing slurry or condensed water droplets deposited onto the bottom surface of the plug. Thus, the endpoint of a CMP process can be precisely determined. Consequently, the yield of the manufacturing process for integrated circuits is substantially improved and the cost of fabrication is significantly reduced.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.


REFERENCES:
patent: 5433651 (1995-07-01), Lustig et al.
patent: 6045439 (2000-04-01), Birang et al.

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