Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2002-03-15
2003-10-28
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S297000
Reexamination Certificate
active
06639436
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor integrated circuits, and particularly relates to a semiconductor integrated circuit equipped with a clock control circuit for starting and stopping the supply of a clock signal to an internal circuit. The present invention further relates to a clock control method that starts and stops the supply of a clock signal to an internal circuit.
2. Description of the Related Art
In large-scale logic circuits such as semiconductor integrated circuits, a technology for controlling the supply of clock signals inside circuitry is important in terms of the reduction of power consumption. In particular, such technology is widely used for portable equipment, for which power consumption is a vital consideration.
In general, the control of starting and stopping of clock supply is not explicitly taken care of by the system, but rather the supply of clock signals is started and stopped in conjunction with the power-on and the power-off of the system. As the circuit size increases and portable equipment becomes ever widely used, standby power consumed by the load capacitance associated with clock wires becomes conspicuous and cannot be ignored. As a result, it has become routine to control the starting and stopping of clock signals by use of gated clocks.
In the related-art clock control, a clock control unit is connected to the bus of a micro-controller, and is used to control the starting and stopping of clock signals with respect to functional blocks connected to the bus. The clock control unit may be provided with registers corresponding to respective functional blocks, and the control of clock signals for the functional blocks is performed by using the micro-controller to store commands regarding clock supply and suspension in the respective registers.
In the control scheme as described above, the starting and stopping of clock signals are controlled at the timing that is indicated by the micro-controller. In order to control the clock signals in accordance with the start and stop of operations of the functional blocks, the micro-controller needs to check the operation status of individual functional blocks constantly. To achieve this, it is necessary to conduct polling to each functional block at short intervals. This is not practical. In practice, thus, a unit of control regarding the starting and stopping of clock supply is set to a relatively large logic circuit block, thereby making it feasible to control clocks at relatively long check cycles.
Now that a single LSI can accommodate several million gates because of the development of semiconductor manufacturing technology, it is common to implement an entire system on a single LSI. In such a configuration, a large number of functional blocks are provided inside the single LSI. In the related-art configuration as described above, it is difficult to reduce the block size of the unit of clock control and to control clocks at short processing intervals because of the processing load of the micro-controller. This is a factor that hampers efforts toward a reduction of power consumption.
Accordingly, there is a need for a semiconductor integrated circuit provided with a clock control circuit that effectively controls the starting and stopping of clock supply on a functional-block-specific basis, and a need for a clock-control method for controlling the starting and stopping of clock supply on a functional-block-specific basis.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a semiconductor integrated circuit that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a semiconductor integrated circuit particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a semiconductor integrated circuit according to the present invention includes a plurality of functional blocks, each of which starts and stops an operation thereof in response to assertion and negation, respectively, of a corresponding command signal, a clock generation circuit which generates a clock signal, a clock control circuit which starts supplying the clock signal to each of the functional blocks in response to the assertion of the corresponding command signal, and stops supplying the clock signal to each of the functional blocks in response to the negation of the corresponding command signal.
In the semiconductor integrated circuit described above, the control of starting and stopping of clock supply to each block is carried out in response to a command signal corresponding to each block that orders the starting and stopping of an operation of each block. In this configuration, it is not the micro-controller that determines the start and halt timing of clock supply. Because of this, even when the unit of clock control is reduced in size to increase the number of blocks, the micro-controller will not suffer an increase of the load. Further, the timing of starting and stopping of clock supply can be diligently controlled to reflect the start and halt of actual operations of functional blocks, regardless of processing cycles of the micro-controller.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.
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patent: 5834961 (1998-11-01), Hillan et al.
patent: 6020774 (2000-02-01), Chiu et al.
patent: 6462599 (2002-10-01), Nitta et al.
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patent: 2000-293504 (2000-10-01), None
patent: 2000-347761 (2000-12-01), None
Kanasugi Masami
Kuroiwa Koichi
Taniguchi Shoji
Yamada Yoshikazu
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